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xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor preliminary specification supersedes data of 1999 dec 20 2000 jan 25 integrated circuits philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 i general description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features in common with xa-g3 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xa-c3 specific features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xa-c3 can and ctl features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic symbol and block diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . upgrading xa-g3 designs to can 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-pin plcc package 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-pin lqfp package 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic symbol 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin descriptions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . special function registers 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory-mapped registers 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xa-c3 timer/counters 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer 0 and timer 1 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . new enhanced mode 0 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode 1 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode 2 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode 3 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . new timer-overflow toggle output 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer t2 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capture mode 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . auto-reload mode (up or down counter) 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . baud rate generator mode 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programmable clock-out 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog timer 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog function 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog control register (wdcon) 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog detailed operation 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . wdcon register bit definitions 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uart 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial port control register 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit interrupt flag 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-bit mode 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bypassing double-buffering 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clocking scheme and baud rate generation 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock rates for all uart modes 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . baud rates for uart modes 0 and 2 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . baud rate calculations for uart modes 0 and 2 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . baud rates for uart modes 1 and 3 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . baud rate calculations for uart modes 1 and 3 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . baud rate calculations for uart mode 1 and 3: 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . using timer 2 to generate baud rates 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uart interrupt scheme 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multiprocessor communications 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . error handling, status flags and break detect 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic address recognition 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input/output port pin configuration 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external bus 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rst/pin properties and requirements 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-on reset 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . other reset effects 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 ii reset timing 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power reduction modes 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupts 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt types 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt structures 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . event interrupt handling 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt priority details 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc electrical characteristics 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac electrical characteristics 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eprom characteristics 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . security bits 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xa-c3 overview 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . introduction 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . definition of terms 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . standard and extended can frames 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . acceptance filtering 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message object 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can arbitration id 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . screener id 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . match id 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mask 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctl 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fragmented message 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message buffer 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mmr 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ctl/can functionality of the xa-c3 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message objects / message management 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . acceptance filtering 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message storage 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit prearbitration 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . remote frame handling 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory maps 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data memory space 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . code memory space 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can core block (ccb) 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can bus timing 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can system clock 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . samples per bit 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . location of sample point 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . synchronization jump width 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . canbtr: can bus timing register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can command and status registers 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . two modes in can core operation 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cancmr: can command register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . canstr: can status register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can/ctl message handler 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message objects 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive message objects and the receive process 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . acceptance filtering 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message storage 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message assembly 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit message objects and the transmit process 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . prearbitration based on priority (default mode) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 iii prearbitration based on object number 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message retrieval 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmission of fragmented messages 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rtr handling 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receiving an rtr frame 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmitting an rtr frame 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data integrity issues 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . using the semaphore bits, sem1 and sem0 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . avoiding data corruption for transmit message objects 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . osek, devicenet, and canopen frames of interest 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . osek consecutiveframe 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . devicenet i/o message 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . canopen download domain segment request 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . canopen autoacknowledge tx response to download domain segment 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can/ctl related interrupts 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx and tx message complete interrupts 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx buffer full interrupt 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . message error interrupt 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tx buffer underflow 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fragmentation error 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . frame error interrupt 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus error 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . prebuffer overflow 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . arbitration lost 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . error warning 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . error passive 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus off 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can interrupt registers 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . canintflg (can interrupt flag register) 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . festr (frame error status register) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . feenr (frame error enable register) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mcir (message complete info register) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . meir (message error info register) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mcplh (message complete status flags high) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mcpll (message complete status flags low) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . txerc (tx error counter) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rxerc (rx error counter) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ewlr (error warning limit register) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eccr (error code capture register) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . alcr (arbitration lost capture register) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can interrupt sfrs 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . powerdown and idle mode 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . background: xa powerdown and idle modes 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xa-c3 idle mode 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xa-c3 powerdown mode 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . can sleep enable 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory interface unit 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general description 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . summary of features 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory mapped registers (mmrs) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . special function register mrbh 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . special function register mrbl 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . onchip message buffer ram (xram) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mbxsr (message buffer and xram segment register) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 iv xramb (xram base address) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mif control and configuration registers 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mifcntl (sfr) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mifbtrl (memory interface bus timing register low, mmr) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mifbtrh (memory interface bus timing register high, mmr) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus arbitration 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . spi port 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . spicfg (mmr) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . spidata (mmr) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . spics (mmr) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 v list of figures figure 1. 44-pin plcc package 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 2. 44-pin plcc package 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 3. logic symbol 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 4. xa-c3 simplified block diagram 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 5. system configuration register (scr) 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 6. timer/counter mode control (tmod) register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 7. timer/counter control (tcon) register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 8. timer/counter 2 control (t2con) register 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 9. timer 0 and 1 extended status (tstat) 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 10. timer 2 mode control (t2mod) 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 11. timer 2 in capture mode 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 12. timer 2 in auto-reload mode (dcen = 0) 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 13. timer 2 auto reload mode (dcen = 1) 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 14. watchdog timer in xa-c3 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 15. serial port extended status (s0stat) register 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 16. serial port control (s0con) register 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 17. uart framing error detection 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 18. uart multiprocessor communication, automatic address recognition 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 19. recommended reset circuit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 20. ea/ timing diagram 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 21. external program memory read cycle (ale cycle) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 22. external program memory read cycle (non-ale cycle) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 23. external data memory read cycle (ale cycle) 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 24. external data memory write cycle 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 25. wait signal timing 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 26. external clock drive 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 27. ac testing input/output 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 28. float waveform 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 29. idd test condition, active mode 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 30. idd test condition, idle mode 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 31. idd vs. frequency at vdd = 5.0v 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 32. clock signal waveform for idd tests in active and idle modes 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 33. idd test condition, power-down mode 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 34. interleaved can data frames 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 35. can frame formats 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 36. mmrs and xram mapped into segment 00h. 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 37. external code memory starts at 008000h. 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 38. memory image for nonfragmented messages 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 39. retrieving the screener id for an extended can frame 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 40. memory image for fragmented ctl messages (frag = 1 and prtcl1 prtcl0 p 00) 43 . . . . . . . . . . . . . . . . . . . . . . figure 41. memory image for can frame buffering (frag = 1 and prtcl1 prtcl0 = 00) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 42. format for storing the tx frame info in mnmskh 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 43. formation of the mmr base address 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 44. detail of mmr space showing block of message object registers 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 45. formation of the xram base address, with object n message buffer mapped to offchip data memory. 56 . . . . . figure 46. object n message buffer mapped into the onchip xram. 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 vi list of tables table 1. ordering information 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 2. 44-pin plcc package pin functions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 3. 44-pin lqfp package pin functions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 4. pin descriptions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 5. special function registers 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 6. memory-mapped registers 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 7. timer 2 operating modes 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 8. prescalar select values in wdcon 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 10. t2con settings 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 11. prescaler select for timer clock 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 12. vector locations for uart in xa 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 13. port configuration register settings 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 14. interrupt priority levels 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 15. exception and trap interrupt vectors 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 16. event interrupt vectors 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 17. software interrupt vectors 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 18. absolute maximum ratings 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 19. dc electrical characteristics 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 20. ac electrical characteristics 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 21. program security bits 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 22. message object register functions for tx and rx 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 23. allowable message buffer sizes 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 24. format for storing the canopen acknowledge byte 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 25. error codes for the error code capture register (eccr) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 26. arbitration lost codes 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 27. sfr interrupt enable/priority bit positions 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 1 2000 jan 25 general description the xac3 is a member of the philips xa (extended architecture) family of highperformance 16bit singlechip microcontrollers. the xac3 combines an array of standard peripherals together with a pelican can 2.0b engine and unique omessage managemento hardware to provide integrated support for most can transport layer (ctl) protocols such as devicenet, canopen and osek. for additional details, refer to the xa-c3 overview on page 35. the xa architecture supports: easy 16-bit migration from the 80c51 architecture. 16bit fully static cpu with 24bit addressed program and data spaces. twentyone 16bit cpu core registers capable of all arithmetic and logic operations while serving as memory pointers. an enhanced orthogonal instruction set tailored for highlevel support of the c language. multitasking and direct realtime executive support. lowpower operation intrinsic to the xa architecture includes powerdown and idle modes. features in common with xa-g3 pincompatibility (can rxd and can txd use the xa-g3 nc pins). 32k bytes of onchip eprom program memory (see table 1). 44pin plcc (figure 1 and table 2) and 44pin lqfp (figure 2 and table 3) packages. commercial (0 to 70 o c) and industrial (40 to 85 o c) ranges. supports offchip addressing of program and data memory up to 1 megabyte each (20 address lines). three standard counter/timers (t0, t1, and t2) with enhancements such as auto reload for pwm outputs. uart0 with enhancements such as separate rx and tx interrupts, break detection, and automatic address recognition. watchdog with a secure wfeed1 / wfeed2 sequence. four 8bit i/o ports with 4 programmable output configurations per pin. xa-c3 specific features 32 mhz operating frequency at 4.5 to 5.5v operation. one serial port interface (spi) 1024 bytes of onchip data ram. 42 vectored interrupts. these include 13 maskable events, 7 software interrupts, 6 exceptions, 16 software traps, segmented data memory, multiple user stacks, and banked registers to support rapid context switching. external interfacing via a 16bit data bus width. xa-c3 can and ctl features a pelican can 2.0b engine from the sja1000 standalone can controller which supports 11 and 29bit identifiers and the maximum can data rate (1 mbps) and can diagnostics. hardware amessage managemento support for all major ctl protocols: devicenet, canopen, osek. automatic (hardware) assembly of fragmented messages via a transport layer co-processor. concurrent assembly of up to 32 separate interleaved fragmented messages 32 can transport layer (ctl) message objects are modelled as a fullcan object superset. 32 separate filters/screeners (one per message object), each allowing a 30bit id match and full 29bit mask (i.e., each filter/screener represents a unique group address). each message object can be configured as receive or transmit. a separate message buffer is associated with each ctl message object. 32 message buffers are located in xram and managed by 32 dma channels. message buffer size for each message object is independently configurable in length (from 2 to 256 bytes). for singlechip systems there is a 512byte (onchip) xram message buffer, independent of the 1k onchip data ram, which is extendable (offchip) to 8k bytes (i.e., 32 message objects that can be up to 256 bytes each). logic symbol and block diagram refer to figure 3 for the logic symbol for the xa-c3 and to figure 4 for a simplified block diagram representation. upgrading xa-g3 designs to can xa-g3 nc pins are xa-c3 can rxd and can txd pins. xa-g3 uart1 is replaced by a serial port interface (spi) xa-c3 software must never write to the bcr register xa-c3 software must initialize btrh and btrl with 00h philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 2 ordering information table 1. ordering information xac3 type & part number temperature range (degrees c) package description operating frequency (mhz) drawing number otp pxac37kbbd 0 to +70 low profile pqfp [lqfp44] 32 sot3891 pxac37kba 0 to +70 plcc [plcc44] 32 sot1872 pxac37kfbd 40 to +85 low profile pqfp [lqfp44] 32 sot3891 pxac37kfa 40 to +85 plcc [plcc44] 32 sot1872 philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 3 pin configurations 44-pin plcc package figure 1. 44-pin plcc package table 2. 44-pin plcc package pin functions pin function (see note) pin function (see note) 1 v ss 23 v dd 2 p1.0 ; wrh / 4 p2.0 ; a12d8 3 p1.1 ; a1 25 p2.1 ; a13d9 4 p1.2 ; a2 26 p2.2 ; a14d10 5 p1.3 ; a3 27 p2.3 ; a15d11 6 p1.4 ; spirx 28 p2.4 ; a16d12 7 p1.5 ; spitx 29 p2.5 ; a17d13 8 p1.6 ; t2 ; spiclk 30 p2.6 ; a18d14 9 p1.7 ; t2ex 31 p2.7 ; a19d15 10 rst / 32 psen / 11 p3.0 ; rxd0 33 ale ; prog / 12 can rxd 34 can txd 13 p3.1 ; txd0 35 ea / ; vpp ; wait 14 p3.2 ; int0 / 36 p0.7 ; a11d7 15 p3.3 ; int1 / 37 p0.6 ; a10d6 16 p3.4 ; t0 38 p0.5 ; a9d5 17 p3.5 ; t1 39 p0.4 ; a8d4 18 p3.6 ; wrl / 40 p0.3 ; a7d3 19 p3.7 ; rd / 41 p0.2 ; a6d2 20 xtal2 42 p0.1 ; a5d1 21 xtal1 43 p0.0 ; a4d0 22 v ss 44 v dd note: 1. all activelow signals are indicated by a a / o symbol philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 4 44-pin lqfp package figure 2. 44-pin plcc package table 3. 44-pin lqfp package pin functions pin function (see note) pin function (see note) 1 p1.5 ; spitx 23 p2.5 ; a17d13 2 p1.6 ; t2 ; spiclk 4 p2.6 ; a18d14 3 p1.7 ; t2ex 25 p2.7 ; a19d15 4 rst / 26 psen / 5 p3.0 ; rxd0 27 ale ; prog / 6 can rxd 28 can txd 7 p3.1 ; txd0 29 ea / ; vpp ; wait 8 p3.2 ; int0 / 30 p0.7 ; a11d7 9 p3.3 ; int1 / 31 p0.6 ; a10d6 10 p3.4 ; t0 32 p0.5 ; a9d5 11 p3.5 ; t1 33 p0.4 ; a8d4 12 p3.6 ; wrl / 34 p0.3 ; a7d3 13 p3.7 ; rd / 35 p0.2 ; a6d2 14 xtal2 36 p0.1 ; a5d1 15 xtal1 37 p0.0 ; a4d0 16 vss 38 vdd 17 vdd 39 vss 18 p2.0 ; a12d8 40 p1.0 ; wrh / 19 p2.1 ; a13d9 41 p1.1 ; a1 20 p2.2 ; a14d10 42 p1.2 ; a2 21 p2.3 ; a15d11 43 p1.3 ; a3 22 p2.4 ; a16d12 44 p1.4 ; spirx note: 1. all activelow signals are indicated by a a / o symbol philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 5 logic symbol v dd v ss xtal1 xtal2 rst/ v pp ; wait; ea/ t2/spiclk t2ex; int2/ a3 a2 su01316 a1 wrh/ port 1 port 2 psen/ ale; prog/ port 0 address bus port 3 t0 t1 wrl/ rd/ rxd0 txd0 int0/ int1/ alternate functions spitx spir x can tx can rx address and 16-bit data bus including 32 dma channels for 32 cal message objects figure 3. logic symbol philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 6 block diagram xa cpu core sfr bus 32k bytes otp 1024 bytes data ram 512 bytes xram ctl message objects 32 ctl dma channels 32 object ptrs 32 id filters 2.0b can/dll pelican core uart0 spi timer 0 timer 1 timer 2 watchdog timer su01317 program bus data bus ports 03 memory interface core data bus mmr bus external address / data bus can rxd can txd figure 4. xa-c3 simplified block diagram philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 7 pin descriptions table 4. pin descriptions mnemonic pin numbers type name and function plcc lqfp v ss 1, 22 16, 39 i ground: 0v reference. v dd 23, 44 17, 38 i power supply: this is the power supply voltage for normal, idle and powerdown op- eration. p0.0 p0.7 43 36 3730 i/o port 0: port 0 is an 8bit i/o port with user configurable pins. port 0 latches have 1's written to them and are configured in the quasibidirectional mode during reset. the operation of port 0 pins as inputs or outputs depends upon the port configuration se- lected. each port pin is configured independently. refer to the sections on i/o port configuration and dc electrical characteristics for details. note: 2. when the external program/data bus is used, port 0 becomes the multiplexed low data/instruction byte and address lines 4 through 11. p1.0 p1.7 2 9 40 44 1 3 i/o port 1: port 1 is an 8bit i/o port with user configurable pins. port 1 latches have 1's written to them and are configured in the quasibidirectional mode during reset. the operation of port 1 pins as inputs or outputs depends upon the port configuration se- lected. each port pin is configured independently. refer to the sections on i/o port configuration and dc electrical characteristics for details. p1.0 2 40 o wrh / : address bit 0 of the external address bus when the external data bus is config- ured for 8bit width. when the external data bus is used, this pin becomes the high byte write strobe (wrh). p1.1 3 41 o a1: address bit 1 of the external address bus. p1.2 4 42 o a2: address bit 2 of the external address bus. p1.3 5 43 o a3: address bit 3 of the external address bus. p1.4 6 44 i spirx: receiver serial input of spi. p1.5 7 1 o spitx: transmitter serial output of spi. p1.6 8 2 i t2 ; spiclk: timer/counter 2 external clock input or timer/counter 2 clockout mode output, or spi clock output. notes: 3. spiclk must be configured to idle in the logic `1' state in order to use either the t2 or p1.6 output functions, even if the spi port is not in use! 4. the default state from reset of the spiclk polarity is ainvertedo which yields an spiclk idle state of logic `1'. 5. if the spi clock polarity is changed by the user during spi port usage, it must be restored to ainvertedo polarity before using either the p1.6 or timer/counter 2 output functions. p1.7 9 3 o t2ex: timer/counter 2 reload/capture/direction control. p2.0 p2.7 24 31 18 25 i/o port 2: port 2 is an 8bit i/o port with userconfigurable pins. port 2 latches have 1's written to them and are configured in the quasibidirectional mode during reset. the operation of port 2 pins as inputs or outputs depends upon the port configuration se- lected. each port pin is configured independently. refer to the sections on i/o port configuration and dc electrical characteristics for de- tails. notes: 6. when the external 16bit program/data bus is used, port 2 is muxed between high (data/instruction) byte and address lines 12 through 19. p3.0 p3.7 11, 13 19 5, 7 12 i/o port 3: port 3 is an 8bit i/o port with userconfigurable pins. notes: 7. port 3 latches have 1's written to them and are configured in the quasibidirectional mode during reset. 8. the operation of port 3 pins as inputs or outputs depends upon the port configuration selected. 9. each port pin is configured independently. refer to the sections on i/o port configuration and dc electrical characteristics for details. p3.0 11 5 i rxd0: receiver serial input of uart 0. p3.1 13 7 o txd0: transmitter serial output of uart 0. p3.2 14 8 i int0 / : external interrupt 0 input. p3.3 15 9 i int1 / : external interrupt 1 input. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 8 mnemonic name and function type pin numbers lqfp plcc p3.4 16 10 i/o t0: timer 0 external count input or timer 0 overflow output. p3.5 17 11 i/o t1 : timer 1 external count input or timer 1 overflow output. p3.6 18 12 o wrl / : external data memory low byte write strobe. p3.7 19 13 o rd / : external data memory read strobe. rst / 10 4 i reset / : note: 10. a low on this pin resets the xac3, causing i/o ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. refer to the reset section for details. ale ; prog / 33 27 i/o address latch enable ; program pulse / : notes: 11. a high output on the ale pin signals external circuitry to latch the address portion of the multiplexed address/data bus. 12. a pulse on ale occurs only when needed to process an external bus cycle. during eprom programming, this pin is used as the program pulse input. psen / 32 26 o program store enable / : this is the read strobe for external program memory. notes: 13. when the microcontroller accesses external program memory, psen / is driven low in order to enable memory devices. 14. psen / is only active when external code accesses are performed. ea / ; wait ; v pp 35 29 i external access / ; wait ; programming supply voltage: notes: 15. the ea / input determines whether the internal program memory of the xac3 is used for code execution. 16. the ea / pin is latched as the (external) reset input is released and its value applied during later execution. when latched as a 0, external program memory is used exclusively. when latched as a 1, internal program memory will be used up to its limit, and external program memory is used above that point. 17. after reset is released, this pin takes on the function of a bus wait input. if wait is asserted high during any external bus access, that cycle will be extended until wait is released. 18. during eprom programming, this pin is also the programming supply voltage input. can rxd 12 6 i can receive data input: can serial receiver input to the sja1000 pelican core. can txd 34 28 o can transmit data output: can serial transmitter output from the sja1000 pelican core. xtal1 21 15 i crystal 1: input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. xtal2 20 14 o crystal 2: output from the oscillator amplifier. note: 1. all activelow signals are indicated by a a/o symbol. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 9 special function registers table 5. special function registers name description sfr bit functions and bit addresses reset address 7 6 5 4 3 2 1 0 value bcr bus configuration register 46ah waitd busd 07h (note 1) btrh bus timing register high 469h dw1 dw0 dwa1 dwa0 dr1 dr0 dra1 dra0 ffh (note 2) btrl bus timing register low 468h wm1 wm0 alew cr1 cr0 cra1 cra0 efh (note 2) mifcntl mif control register 495h wdsbl busd mrbl mmr base address low 496h ma15 ma14 ma13 ma12 mrbe f0h mrbh mmr base address high 497h ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 0fh ds data segment 441h 00h es extra segment 442h 00h cs code segment 443h 00h 33f 33e 33d 33c 33b 33a 339 338 ieh* interrupt enable high 427h emri emti emer ecer espi eti0 eri0 00h 337 336 335 334 333 332 331 330 iel* interrupt enable low 426h ea ebuff et2 et1 ex1 et0 ex0 00h ipa0 interrupt priority assignment 0 4a0h pt0 px0 00h ipa1 interrupt priority assignment 1 4a1h pt1 px1 00h ipa2 interrupt priority assignment 2 4a2h pbuff pt2 00h ipa4 interrupt priority assignment 4 4a4h pti0 pri0 00h ipa5 interrupt priority assignment 5 4a5h pspi 00h ipa6 interrupt priority assignment 6 4a6h pmer pcer 00h ipa7 interrupt priority assignment 7 4a7h pmri pmti 00h 387 386 385 384 383 382 381 380 p0* port 0 430h a11d7 a10d6 a9d5 a8d4 a7d3 a6d2 a5d1 a4d0 ffh 38f 38e 38d 38c 38b 38a 389 388 p1* port 1 431h t2ex t2 ; spiclk spitx spirx a3 a2 a1 wrh / ffh 397 396 395 394 393 392 391 390 p2* port 2 432h a19d15 a18d14 a17d13 a16d12 a15d11 a14d10 a13d9 a12d8 ffh 39f 39e 39d 39c 39b 39a 399 398 p3* port 3 433h rd / wrl / t1 t0 int1 / int0 / txd0 rxd0 ffh p0cfga port 0 configuration a 470h note 3 p1cfga port 1 configuration a 471h note 3 p2cfga port 2 configuration a 472h note 3 p3cfga port 3 configuration a 473h note 3 p0cfgb port 0 configuration b 4f0h note 3 p1cfgb port 1 configuration b 4f1h note 3 p2cfgb port 2 configuration b 4f2h note 3 p3cfgb port 3 configuration b 4f3h note 3 227 226 225 224 223 222 221 220 pcon* power control reg 404h pd idl 00h 20f 20e 20d 20c 20b 20a 209 208 pswh* program status word high 401h sm tm rs1 rs0 im3 im2 im1 im0 note 4 207 206 205 204 203 202 201 200 pswl* program status word low 400h c ac v n z note 4 217 216 215 214 213 212 211 210 psw51* 80c51compatible psw 402h c ac f0 rs1 rs0 v f1 p note 5 rth0 timer 0 extended reload, high byte 455h 00h rth1 timer 1 extended reload, high byte 457h 00h rtl0 timer 0 extended reload, low byte 454h 00h rtl1 timer 1 extended reload, low byte 456h 00h 307 306 305 304 303 302 301 300 s0con* serial port 0 control register 420h sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00h philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 10 name reset bit functions and bit addresses sfr description value 0 1 2 3 4 5 6 7 address 30f 30e 30d 30c 30b 30a 309 308 s0stat* serial port 0 extended status 421h fe0 br0 oe0 stint0 00h s0buf serial port 0 buffer register 460h xxh s0addr serial port 0 address register 461h 00h s0aden serial port 0 address enable register 462h 00h scr system configuration register 440h pt1 pt0 cm pz 00h 21f 21e 21d 21c 21b 21a 219 218 ssel* segment selection register 403h eswen r6seg r5seg r4seg r3seg r2seg r1seg r0seg 00h swe software interrupt enable 47ah swe7 swe6 swe5 swe4 swe3 swe2 swe1 00h 357 356 355 354 353 352 351 350 swr* software interrupt request 42ah swr7 swr6 swr5 swr4 swr3 swr2 swr1 00h 2c7 2c6 2c5 2c4 2c3 2c2 2c1 2c0 t2con* timer 2 control register 418h tf2 exf2 rclk0 tclk0 exen2 tr2 c2 or t2 / cp or rl2 / 00h 2cf 2ce 2cd 2cc 2cb 2ca 2c9 2c8 t2mod* timer 2 mode control 419h t2oe dcen 00h th2 timer 2 high byte 459h 00h tl2 timer 2 low byte 458h 00h t2caph timer 2 capture register, high byte 45bh 00h t2capl timer 2 capture register, low byte 45ah 00h 287 286 285 284 283 282 281 280 tcon* timer 0 and 1 control register 410h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 high byte 451h 00h th1 timer 1 high byte 453h 00h tl0 timer 0 low byte 450h 00h tl1 timer 1 low byte 452h 00h tmod timer 0 and 1 mode control 45ch gate1 c1 or t1 / m1 m0 gate0 c0 or t0 / m1 m0 00h 28f 28e 28d 28c 28b 28a 289 288 tstat* timer 0 and 1 extended status 411h t1oe t0oe 00h 2ff 2fe 2fd 2fc 2fb 2fa 2f9 2f8 wdcon* watchdog control register 41fh pre2 pre1 pre0 wdrun wdtof note 6 wdl watchdog timer reload 45fh 00h wfeed1 watchdog feed 1 45dh xxh wfeed2 watchdog feed 2 45eh xxh notes: 1. users should never write to the bcr register. 2. users must always initialize (write) 00h to this register. 3. port configurations default to quasibidirectional when the xa begins execution from internal code memory after reset, based on the condition found on the ea / pin. thus, all pncfga registers will contain ffh and pncfgb registers will contain 00h. when the xa begins execution using external code memory, the default configuration for pins that are associated with the external bus will be push pull. the pncfga and pncfgb register contents will reflect this difference. 4. sfr is loaded from the reset vector. 5. all bits except f1, f0, and p are loaded from the reset vector. those bits are all 0. 6. the wdcon reset value is e6h for a watchdog reset, e4h for all other reset causes. the watchdog is always turned on as one consequence of rst / . therefore, the user should turn off the watchdog if immediate watchdog operation is not desired: see the watchdog timer section in this data sheet for a recommended code example. general notes: sfrs marked with an asterisk (*) are bitaddressable. the xac3 implements an 8bit sfr bus, as stated in chapter 8 of the xa user guide . all sfr accesses must be 8bit operations. attempts to write 16 bits to an sfr will actually write only the lower 8 bits. sixteenbit sfr reads will return undefined data in the upper byte. unimplemented bits in sfrs (indicated by oo} are unknown at all times. ones should not be written to these bits since they ma y be used for other purposes in future xa derivatives. in general, the reset value shown for these unimplemented bits is 00h. the xa guards writes to all sfr bits that can be modified by hardware, including all sfr resident interrupt flags, as well as the wdtof bit in wdcon. this mechanism, called readmodifywrite lockout, prevents loss of an interrupt (or other status) flag if a bit is writt en to directly by hardware between the read and write of an instruction that performs a readmodifywrite operation. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 11 memory-mapped registers table 6. memory-mapped registers name description address offset operation access reset value message object registers (n = 0 31) mnmidh message n match id high 000n 4 n 3 n 2 n 1 n 0 0000b (n0h) r/w word only xxxxh mnmidl message n match id low 000n 4 n 3 n 2 n 1 n 0 0010b (n2h) r/w word only x x00b mnmskh message n mask high 000n 4 n 3 n 2 n 1 n 0 0100b (n4h) r/w word only xxxxh mnmskl message n mask low 000n 4 n 3 n 2 n 1 n 0 0110b (n6h) r/w word only x x000b mnctl message n control 000n 4 n 3 n 2 n 1 n 0 1000b (n8h) r/w byte 00000xxxb mnblr message n buffer location 000n 4 n 3 n 2 n 1 n 0 1010b (nah) r/w word only xxxxh mnbsz message n buffer size 000n 4 n 3 n 2 n 1 n 0 1100b (nch) r/w byte 00000xxxb mnfcr message n fragmentation count 000n 4 n 3 n 2 n 1 n 0 1110b (neh) r/w byte 00xxxxxxb can/ctl interrupt complete (cic) registers mcplh message complete status flags high 226h rc word 0000h mcpll message complete status flags low 224h rc word 0000h canintflg can interrupt flag register 228h rc byte 00h mcir message complete information 229h ro byte 00h meir message error information 22ah ro byte 00h feenr frame error enable 22eh r/w byte 00h festr frame error status 22ch rc byte 00h spi registers spicfg spi configuration 260h r/w byte 00h spidata spi data 262h r/w byte 00h spics spi control and status 263h r/w byte 00h can core block (ccb) registers cancmr can core command 270h r/w* byte 01h (note 1) canstr can core status 271h ro byte 00h canbtr can core bus timing 272h r/w* word 0000h txerc tx error counter 274h r/w* byte 00h rxerc rx error counter 275h r/w* byte 00h ewlr error warning limit 276h r/w byte 96h eccr error code capture 278h ro byte 00h alcr arbitration lost capture 27ah ro byte 00h gctl global control 27eh r/w byte 00h memory interface (mif) registers mifbtrh mif bus timing register high 293h r/w byte ffh mifbtrl mif bus timing register low 292h r/w byte efh mbxsr message buffer and xram segment register 291h r/w byte ffh xramb xram base address 290h r/w byte feh possible operations: r/w = read & write, ro = read only, rc = read then clear via a service routine, w* = writable only while the can core is in reset mode, x = undefined after reset note: 1. slpen (sleep enable), cancmr[3], is writable only when the can core is in normal mode. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 12 xa-c3 timer/counters the xa has two standard 16bit enhanced timer/counters: timer 0 and timer 1. additionally, it has a third 16bit up/down timer/counter, t2. a central timing generator in the xa core provides the timebase for all xa timers and counters. the timer/event counters can perform the following functions: measure time intervals and pulse duration count external events generate interrupt requests generate pwm or timed output waveforms all timer/counters (timer 0, timer 1 and timer 2) can be independently programmed to operate either as timers or event counters. timer 0 and timer 1 are selectable via tmod[6] and tmod[2], respectively. timer 2 is selectable via t2con[1]. all timers may be dynamically read during program execution. all timers count up unless otherwise stated. when running in timer mode (as opposed to counter mode) the base clock rate of all timers, including the watchdog timer, is userprogrammable. the clock driving the timers is called tclk and is determined by the setting of two bits (pt1, pt0) (scr[3:2]) in the system configuration register see table 5. the frequency of tclk may be selected to be the oscillator input divided by 4 (f c /4), the oscillator input divided by 16 (f c /16), or the oscillator input divided by 64 (f c /64). this gives a range of possibilities for the xa timer functions, including baud rate generation and timer 2 capture. note: this single scr rate setting applies to all timers. when timers t0, t1, or t2 are used in the counter mode, the timers will increment whenever a falling edge (hightolow transition) is detected on an external clock pin. these inputs are sampled once every two oscillator cycles, so it can take as many as four oscillator cycles to detect a transition. thus, the maximum count rate that can be supported is f c /4. in general, the duty cycle of the timer clock inputs is not important. however, any high or low state on the timer clock input pins must be present for two oscillator cycles before it is guaranteed to be aseeno by the timer logic. timer 0 and timer 1 these two timer/counters have four operating modes, which are selected by bitpairs (m1, m0) in the tmod register. timer modes 1, 2, and 3 in xa are kept identical to the 80c51 timer modes for code compatibility. only the mode 0 is replaced in the xa by a more powerful 16bit autoreload mode. this gives the xa timers a much larger range when used as time bases. the recommended m1, m0 settings for the different modes are shown in figure 6. eee e pt1 pt0 cm pz pt1 pt0 operating prescaler selection. 0 0 osc/4 0 1 osc/16 1 0 osc/64 1 1 reserved cm compatibility mode allows the xa to execute most translated 80c51 code on the xa. the xa register file must copy the 80c51 mapping to data memory and mimic the 80c51 indirect addressing scheme. pz page zero mode forces all program and data addresses to 16-bits only. this saves stack space and speeds up execution but limits memory access to 64k. su00589 scr address:440 not bit addressable reset value: 00h lsb msb figure 5. system configuration register (scr) gate c1 or t1/ m1 m0 gate c0 or t0/ m1 m0 lsb msb gate gating control when set. timer/counter ano is enabled only while aintn o pin is high and atrno control bit is set. when cleared timer ano is enabled whenever atrno control bit is set. c/t timer or counter selector cleared for timer operation (input from internal system clock.) set for counter operation (input from atno input pin). m1 m0 operating 0 0 16-bit auto-reload timer/counter 0 1 16-bit non-auto-reload timer/counter 1 0 8-bit auto-reload timer/counter 1 1 dual 8-bit timer mode (timer 0 only) su01325 timer 1 timer 0 tmod address:45c not bit addressable reset value: 00h figure 6. timer/counter mode control (tmod) register philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 13 new enhanced mode 0 for timers t0 or t1 the 13bit count mode on the 80c51 (current mode 0) has been replaced in the xa with a 16bit autoreload mode. four additional 8bit data registers (two per timer: rthn and rtln) are created to hold the autoreload values. in this mode, the th overflow will set the tf flag in the tcon register (see figure 7) and cause both the tl and th counters to be loaded from the rtl and rth registers respectively. these new sfrs will also be used to hold the tl reload data in the 8bit autoreload mode (mode 2) instead of th. the overflow rate for timer 0 or timer 1 in mode 0 may be calculated as follows: timer_rate = f osc / (n * (65536 timer_reload_value)) where n = the tclk prescaler value: 4 (default), 16, or 64. mode 1 mode 1 is the 16bit nonauto reload mode. mode 2 mode 2 configures the timer register as an 8bit counter (tln) with automatic reload. overflow from tln not only sets tfn, but also reloads tln with the contents of rtln, which is preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer/counter 0. the overflow rate for timer 0 or timer 1 in mode 2 may be calculated as follows: timer_rate = f osc / (n * (256 timer_reload_value)) where n = the tclk prescaler value: 4, 16, or 64. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. tl0 uses the timer 0 control bits: c0 ; t0 / , gate0, tr0, int0 / and tf0. th0 is locked into a timer function and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the atimer 1o interrupt. mode 3 is provided for applications requiring an extra 8bit timer. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. it0 lsb msb bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. this flag will not be set if t1oe (tstat.2) is set. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter 1 on/off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. this flag will not be set if t0oe (tstat.0) is set. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter 0 on/off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. su00604c ie0 it1 ie1 tr0 tf0 tr1 tf1 tcon address:410 bit addressable reset value: 00h figure 7. timer/counter control (tcon) register philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 14 cp or rl2/ bit symbol function t2con.7 tf2 timer 2 overflow flag. set by hardware on timer/counter overflow. must be cleared by software. tf2 will not be set when rclk0, rclk1, tclk0, tclk1 or t2oe=1. t2con.6 exf2 timer 2 external flag is set when a capture or reload occurs due to a negative transition on t2ex (and exen2 is set). this flag will cause a timer 2 interrupt when this interrupt is enabled. exf2 is cleared by software. t2con.5 rclk0 receive clock flag. t2con.4 tclk0 transmit clock flag. rclk0 and tclk0 are used to select timer 2 overflow rate as a clock source for uart0 instead of timer t1. t2con.3 exen2 timer 2 external enable bit allows a capture or reload to occur due to a negative transition on t2ex. t2con.2 tr2 start=1/stop=0 control for timer 2. t2con.1 c2 or t2/ timer or counter select. 0=internal timer 1=external event counter (falling edge triggered) t2con.0 cp or rl2/ capture/reload flag. if cp/rl2 & exen2=1 captures will occur on negative transitions of t2ex. if cp/rl2=0, exen2=1 auto reloads occur with either timer 2 overflows or negative transitions at t2ex. if rclk or tclk=1 the timer is set to auto reload on timer 2 overflow, this bit has no effect. su001326 c2 or t2/ tr2 exen2 tclk0 rclk0 exf2 tf2 t2con address:418 bit addressable reset value: 00h lsb msb figure 8. timer/counter 2 control (t2con) register new timer-overflow toggle output in the xa, the timer module now has two outputs, which toggle on overflow from the individual timers. the same device pins that are used for the t0 and t1 count inputs are also used for the new overflow outputs. an sfr bit (tnoe in the tstat register see figure 9 is associated with each counter and indicates whether portsfr data or the overflow signal is output to the pin. these outputs could be used in applications for generating variable duty cycle pwm outputs (changing the autoreload register values). also, variable frequency ( f osc /8 to f osc /8,388,608) outputs could be achieved by adjusting the prescaler along with the autoreload register values. timer t2 timer 2 in the xa is a 16bit timer/counter which can operate as either a timer or as an event counter. this is selected by {c2 or t2 / } (t2con[1]) (see figure 8). upon timer t2 overflow/underflow, the tf2 flag is set, which may be used to generate an interrupt. it can be operated in one of three operating modes: autoreload (up or down counting), capture, or as the baud rate generator (for the uart via sfrs t2con and t2mod see figure 10. these modes are shown in table 7. capture mode in the capture mode there are two options which are selected by bit exen2 (t2con[3]). if exen2 = 0, then timer 2 is a 16bit timer or counter, which upon overflowing sets bit tf2 (t2con[7]), the timer 2 overflow bit. this will cause an interrupt when the timer 2 interrupt is enabled. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1to0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 (t2con[6]) to be set. this will cause an interrupt in the same fashion as tf2 when the timer 2 interrupt is enabled. the capture mode is illustrated in figure 11. auto-reload mode (up or down counter) in the autoreload mode, the timer registers are loaded with the 16bit value in t2caph and t2capl when the count overflows. t2caph and t2capl are initialized by software. if the exen2 bit (t2con[3]) is set, the timer registers will also be reloaded and the exf2 flag t2con[6] set when a 1to0 transition occurs at input t2ex. the autoreload mode is shown in figure 12. in this mode, timer 2 can be configured to count up or down. this is done by setting or clearing the dcen (down counter enable) bit t2mod[0] (see table 7). the t2ex pin then controls the count direction. when t2ex is high, the count is in the up direction, when t2ex is low, the count is in the down direction. figure 12 shows timer 2, which will count up automatically, since dcen = 0. in this mode there are two options selected by bit exen2 in the t2con register. if exen2 bit = 0, then timer 2 counts up to ffffh and sets the tf2 (overflow flag) bit t2con[7] upon overflow. this causes the timer 2 registers to be reloaded with the 16bit value in t2capl and t2caph, whose values are preset by software. if exen2 bit t2con[3] = 1, a 16bit reload can be triggered either by an overflow or by a 1to0 transition at input t2ex. this transition also sets the exf2 bit. if enabled, either tf2 bit or exf2 bit can generate the timer 2 interrupt. in figure 13 where the dcen bit = 1; this enables the timer 2 to count up or down. in this mode, the logic level of t2ex pin controls the direction of count. when a logic `1' is applied at pin t2ex, the timer 2 will count up. the timer 2 will overflow at ffffh and set the tf2 bit flag, which can then generate an interrupt if enabled. this timer overflow also causes the 16bit value in t2capl and t2caph to be reloaded into timer registers tl2 and th2, respectively. a logic `0' at pin t2ex causes timer 2 to count down. when counting down, the timer value is compared to the 16bit value contained in t2caph and t2capl. when the value is equal, the philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 15 timer register is loaded with ffff hex. the underflow also sets the tf2 flag, which can generate an interrupt if enabled. the external flag exf2 bit toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution, if needed. the exf2 bit flag does not generate an interrupt in this mode. as the baud rate generator, timer t2 is incremented by tclk. baud rate generator mode by setting the tclk0 and/or rclk0 in t2con, timer 2 can be chosen as the baud rate generator for the transmitter and/or receiver sides of uart0. programmable clock-out a 50% duty cycle clock can be programmed to come out on p1.6. this pin, besides being a regular i/o pin, has two alternate functions. either it can be programmed to input the external clock for timer/counter 2 or to output a 50% duty cycle clock. to configure the timer/counter 2 as a clock generator, bit {c2 or t2 / } (t2con[1]) must be cleared and bit t2oe (t2mod[1]) must be set. bit tr2 (t2con[2]) also must be set to start the timer. the clockout frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (tcap2h, tcap2l) as shown in this equation: tclk 2 (65536tcap2h, tcap2l) in the clockout mode timer 2 rollovers will not generate an interrupt. this is similar to when it is used as a baudrate generator. it is possible to use timer 2 as a baudrate generator and a clock generator simultaneously. note, however, that the baudrate will be 1/8 of the clockout frequency. table 7. timer 2 operating modes bits of special function registers tr2 t2con[2] cp or rl2/ t2con[0] rclk0 or tclk0 t2con[5] or t2con[4] dcen t2mod[0] mode 0 x x x timer off (stopped) 1 0 0 0 16bit autoreload, counting up 1 0 0 1 16bit autoreload, counting up or down depending on t2ex pin 1 1 0 x 16bit capture 1 x 1 x baud rate generator t0oe lsb msb bit symbol function tstat.2 t1oe when 0, this bit allows the t1 pin to clock timer 1 when in the counter mode. when 1, t1 acts as an output and toggles at every timer 1 overflow. tstat.0 t0oe when 0, this bit allows the t0 pin to clock timer 0 when in the counter mode. when 1, t0 acts as an output and toggles at every timer 0 overflow. su00612b e t1oe e e e e e tstat address:411 bit addressable reset value: 00h figure 9. timer 0 and 1 extended status (tstat) dcen bit symbol function t2mod.5 rclk1 receive clock flag. t2mod.4 tclk1 transmit clock flag. rclk1 and tclk1 are used to select timer 2 overflow rate as a clock source for uart1 instead of timer t1. t2mod.1 t2oe when 0, this bit allows the t2 pin to clock timer 2 when in the counter mode. when 1, t2 acts as an output and toggles at every timer 2 overflow. t2mod.0 dcen controls count direction for timer 2 in autoreload mode. dcen=0 counter set to count up only dcen=1 counter set to count up or down, depending on t2ex (see text). su00610b t2oe e e tclk1 rclk1 e e t2mod address:419 bit addressable reset value: 00h lsb msb figure 10. timer 2 mode control (t2mod) philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 16 tclk c2 or t2/ = 0 tr2 control tl2 (8-bits) th2 (8-bits) tf2 t2capl t2caph exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin capture su01327 c2 or t2/ = 1 figure 11. timer 2 in capture mode tclk c2 or t2/ = 0 c2 or t2/ = 1 tr2 control tl2 (8-bits) th2 (8-bits) tf2 t2capl t2caph exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload su01328 figure 12. timer 2 in auto-reload mode (dcen = 0) philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 17 tclk c2 or t2/ = 0 c2 or t2/ = 1 tl2 th2 tr2 control t2 pin su01329 ffh ffh t2capl t2caph (up counting reload value) t2ex pin tf2 interrupt count direction 1 = up 0 = down exf2 overflow (down counting reload value) toggle figure 13. timer 2 auto reload mode (dcen = 1) philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 18 watchdog timer the watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. it is important to note that the watchdog timer is running after any type of reset and must be turned off by user software if the application does not use the watchdog function. watchdog function the watchdog consists of a programmable prescaler and the main timer. the prescaler derives its clock from the tclk source that also drives timers 0, 1, and 2. the watchdog timer subsystem consists of a programmable 13bit prescaler, and an 8bit main timer. the main timer is clocked (decremented) by a tap taken from one of the top 8bits of the prescaler as shown in figure 14. the clock source for the prescaler is the same as tclk (same as the clock source for the timers). thus the main counter can be clocked as often as once every 32 tclks (see table 8). the watchdog generates an underflow signal (and is autoloaded from wdl) when the watchdog is at count 0 and the clock to decrement the watchdog occurs. the watchdog is 8 bits wide and the autoload value can range from 0 to ffh. (the autoload value of 0 is permissible since the prescaler is cleared upon autoload). this leads to the following user design equations: t min = t osc 4 32 (w = 0, n = 4) t max = t osc 64 4096 256 (w = 255, n = 64) t d = t osc n p (w + 1) where t osc is the oscillator period n is the selected prescaler tap value w is the main counter autoload value p is the prescaler value from table 8 t min is the minimum watchdog timeout value (when the autoload value is 0) t max is the maximum timeout value (when the autoload value is ffh) t d is the design timeout value. the watchdog timer is not directly loadable by the user. instead, the value to be loaded into the main timer is held in an autoload register. in order to cause the main timer to be loaded with the appropriate value, a special sequence of software action must take place. this operation is referred to as feeding the watchdog timer. to feed the watchdog, two instructions must be sequentially executed successfully. no intervening sfr accesses are allowed, so interrupts should be disabled before feeding the watchdog. the instructions should move a5h to the wfeed1 register and then 5ah to the wfeed2 register. if wfeed1 is correctly loaded and wfeed2 is not correctly loaded, then an immediate watchdog reset will occur. the program sequence to feed the watchdog timer or cause new wdcon settings to take effect is as follows: clr ea ; disable global interrupts. mov.b wfeed1,#a5h ; do watchdog feed part 1 mov.b wfeed2,#5ah ; do watchdog feed part 2 setb ea ; reenable global interrupts. this sequence assumes that the xa interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence. if an interrupt was allowed to be serviced and the service routine contained any sfr access, it would trigger a watchdog reset. if it is known that no interrupt could occur during the feed sequence, the instructions to disable and reenable interrupts may be removed. the software must be written so that a feed operation takes place every t d seconds from the last feed operation. some tradeoffs may need to be made. it is not advisable to include feed operations in minor loops or in subroutines unless the feed operation is a specific subroutine. to turn the watchdog timer completely off, the following code sequence should be used: mov.b wdcon,#0 ; set wd control register to clear wdrun. mov.b wfeed1,#a5h ; do watchdog feed part 1 mov.b wfeed2,#5ah ; do watchdog feed part 2 this sequence assumes that the watchdog timer is being turned off at the beginning of the user's initialization code and that the xa interrupt system has not yet been enabled. if the watchdog timer is to be turned off at a point when interrupts may be enabled, instructions to disable and reenable interrupts should be added to this sequence. watchdog control register (wdcon) the reset values of the wdcon and wdl registers will be such that the watchdog timer has a timeout period of 4 4096 t osc and the watchdog is running. wdcon can be written by software but the changes only take effect after executing a valid watchdog feed sequence. table 8. prescalar select values in wdcon pre2 pre1 pre0 divisor 0 0 0 32 0 0 1 64 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 1024 1 1 0 2048 1 1 1 4096 watchdog detailed operation when external reset is applied, the following takes place: watchdog run control bit set to on (1). autoload register wdl set to 00 (min. count). watchdog timeout flag cleared. prescaler is cleared. prescaler tap set to the highest divide. autoload takes place. when coming out of a hardware reset, the software should load the autoload register and then feed the watchdog (i.e., cause an autoload). if the watchdog is running and happens to underflow at the time the external reset is applied, the watchdog timeout flag will be cleared. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 19 pre2 pre1 pre0 e e wdrun wdtof wdcon 8bit down counter prescaler tclk mov wfeed1,#a5h mov wfeed2,#5ah watchdog feed sequence wdl su00581a e internal reset figure 14. watchdog timer in xa-c3 when the watchdog underflows, the following action takes place (see figure 14): autoload takes place. watchdog timeout flag is set watchdog run bit unchanged. autoload (wdl) register unchanged. prescaler tap unchanged. all other device action same as external reset. note that if the watchdog underflows, the program counter will be loaded from the reset vector as in the case of an internal reset. the watchdog timeout flag can be examined to determine if the watchdog has caused the reset condition. the watchdog timeout flag bit can be cleared by software. wdcon register bit definitions wdcon[7] pre2 prescaler select 2, reset to 1 wdcon[6] pre1 prescaler select 1, reset to 1 wdcon[5] pre0 prescaler select 0, reset to 1 wdcon[2] wdrun watchdog run control bit, reset to 1 wdcon[1] wdtof timeout flag uart the xac3 includes 1 uart port (uart0) that is compatible with the enhanced uart used on the 8xc51fb. baud rate selection is somewhat different due to the clocking scheme used for the xa timers. four other enhancements have been made to uart operation: first, there are separate interrupt vectors for uart transmit and receive functions. second, the uart0 transmitter has been doublebuffered, allowing packed transmission of data with no gaps between bytes and less critical interrupt service routine timing. third, a break detect function has been added to uart0. this operates independently of the uart and provides a startofbreak status bit that the user program may use to test br0 (s0stat[2]). fourth, an overrun error flag has been added to detect missed characters in the received data stream. the uart baud rate is determined by either a fixed division of the oscillator (in uart0 modes 0 and 2) or by the timer 1 or timer 2 overflow rate (in uart0 modes 1 and 3). timer 1 defaults to clock uart0. timer 2 can clock uart0 through t2con via bits rclk0 (t2con[5]) and/or tclk0 (t2con[4]). the serial port receive and transmit registers are both accessed at special function register s0buf. writing to s0buf loads the transmit register, and reading s0buf accesses the physically separate receive register. the serial port can operate in 4 modes: mode 0: serial i/o expansion mode. serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). (the baud rate is fixed at 1/16 the oscillator frequency.) mode 1: standard 8bit uart mode. 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into bit rb8_0 (s0con[2]). the baud rate is variable via timer 1 or timer 2 overflow rates. mode 2: fixed rate 9bit uart mode. 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit tb8_0 (s0con[3]) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8_0. on receive, the 9th data bit goes into bit rb8_0, while the stop bit is ignored. the baud rate is programmable to 1/32 of the oscillator frequency. mode 3: standard 9bit uart mode. 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable via timer 1 or timer 2 overflow rates. in all four modes, transmission is initiated by any instruction that uses s0buf as a destination register. reception is initiated in mode 0 by the condition ri_0 (s0con[0]) = 0 and ren_0 (s0con[4]) = philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 20 1. reception is initiated in mode 1, 2, or 3 by the incoming start bit if ren_0 = 1. serial port control register the serial port control and status register is the special function register s0con, shown in figure 16. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive tb8_0 (s0con[3]) and rb8_0 (s0con[2]), and the serial port interrupt bits transmit interrupt flag ti_0 (s0con[1]) and receive interrupt flag ri_0 (s0con[0]) . transmit interrupt flag in order to allow easy use of the doublebuffered uart0 transmitter feature, the ti_0 flag is set by the uart0 hardware under two conditions. the first condition is the completion of any byte transmission. this occurs at the end of the stop bit in modes 1, 2, or 3, or at the end of the eighth data bit in mode 0. the second condition is when s0buf is written while the uart0 transmitter is idle. generally, uart transmitters generate one interrupt per byte transmitted. however, uart0 generates one additional interrupt (as defined by the stated conditions for setting the ti_0 flag). this additional interrupt does not occur if doublebuffering is bypassed as explained below. note: if characteroriented transmission is used (not blocktransmission of characters), there could be a second interrupt for each character transmitted, depending on the timing of the writes to s0buf. for this reason, it is generally better to bypass doublebuffering when uart0 is used in characteroriented mode. this is also true if uart0 is polled rather than interruptdriven. the interrupt occurs at the end of the last byte transmitted when the uart becomes idle. among other things, this allows a program to determine when a message has been transmitted completely. the interrupt service routine should handle this additional interrupt. the recommended way to use transmit doublebuffering in an application program is to have the uart interrupt service routine handle a single byte for each interrupt occurrence. thus, the program will not require any special considerations for doublebuffering. transmitted bytes will then be tightly packed with no intervening gaps. note: be aware that higher priority interrupts may cause delays in servicing a transmitter interrupt, and this would defeat doublebuffering. 9-bit mode because the ninth data bit tb8_0 (s0con[3]) is not doublebuffered, you must insure s0con[3] contains the intended ninth data bit whenever it is transmitted. alternatively, to synchronize the ninth data bit with the rest of the data stream, you could bypass doublebuffering. bypassing double-buffering the uart transmitter may be used as if it is singlebuffered. the recommended uart transmitter interrupt service routine (isr) technique to bypass doublebuffering first clears the ti_0 flag (s0con[1]) upon entry into the isr, as in standard practice. this clears the interrupt that activated the isr. secondly, the ti_0 flag is cleared immediately following each write to s0buf. this clears the interrupt flag that would otherwise direct the program to write to the second transmitter buffer. if there is any possibility that a higher priority interrupt might become active between the write to s0buf and the clearing of the ti_0 flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the ea bit (iel[7]). clocking scheme and baud rate generation clock rates for all uart modes for uart modes 0 and 2 the uart clock rate is determined by a fixed division of the oscillator clock. for modes 1 and 3 the uart clock rate is determined by the overflow rates of either t1 or t2. baud rates for uart modes 0 and 2 in uart mode 0, the baud rate is fixed at f osc /16. in mode 2, however, it is fixed rate at f osc /32. baud rate calculations for uart modes 0 and 2 baud rate for uart mode 0: baud_rate = f osc /16 baud rate for uart mode 2: baud_rate = f osc /32 baud rates for uart modes 1 and 3 table 9 shows the relationship of tclk to prescalar settings for all timers t0, t1, and t2. table 9. tclk frequencies prescalar value pt1 ; scr[3] pt0 ; scr[2] tclk 4 0 0 f osc /4 16 0 1 f osc /16 64 1 0 f osc /64 1 1 reserved thus, when timers t0, t1, and t2 are used to establish the baud rate for baud clock, the maximum speed of timers/(baud clock) is f osc /4 (since the minimum prescalar value n is equal to 4). consequently, the maximum baud_rate equals timer_rate (timer overflow) divided by 16, i.e., f osc /64. baud rate calculations for uart modes 1 and 3 baud rate calculations for uart mode 1 and 3: baud_rate = timer_rate/16 timer_rate = f osc /(n x (timer_range timer_reload_value)) where n = the tclk prescaler value (4, 16, or 64). and timer_range = 256 for timer 1 in mode 2. and timer_range = 65536 for timer 1 in mode 0 and timer 2 in countup mode. the timer reload value may be calculated as follows: timer_reload_value = timer_range (f osc /(baud_rate*n*16)) notes: 1. the maximum baud rate for uart0 in mode 1 or 3 is f osc /64. 2. the lowest possible baud rate (for a given oscillator frequency and n value) may be found by using a timer reload value of 0. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 21 3. the timer reload value may never be larger than the timer range. 4. if a timer reload value calculation gives a negative or fractional result, the baud rate requested is not possible at the given oscillator frequency and n value. using timer 2 to generate baud rates timer t2 is a 16bit up/down counter. as a baud rate generator, timer 2 is selected as a clock source for uart0 transmitter and/or receiver by setting tclk0 and/or rclk0 in t2con (see table 10). as the baud rate generator, t2 is incremented as f osc /n where n = 4, 16, or 64 depending on tclk as programmed in scr bits pt1 (scr[3]) and pto (scr[2]). see table 11). note: pin t2ex [p1.7] acts as an additional external interrupt aint2 / o whenever timer t2 is used as a baud rate generator. table 10. t2con settings t2con 0x418 t2con[5] t2con[4] rclk0 tclk0 table 11. prescaler select for timer clock scr 0x440 scr[3] scr[2] pt1 pt0 stint0 bit symbol function s0stat.3 fe0 framing error flag is set when the receiver fails to see a valid stop bit at the end of the frame. cleared by software. s0stat.2 br0 break detect flag is set if a character is received with all bits (including stop bit) being logic `0'. thus it gives a astart of break detecto on bit 8 for mode 1 and bit 9 for modes 2 and 3. the break detect feature operates independently of the uarts and provides the start of break detect status bit that a user program may poll. cleared by software. s0stat.1 oe0 overrun error flag is set if a new character is received in the receiver buffer while it is still full (before the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is received while ri_0 in s0con is still set. cleared by software. s0stat.0 stint0 this flag must be set to enable any of the above status flags to generate a receive interrupt (ri_0). the only way it can be cleared is by a software write to this register. su01315 oe0 br0 fe0 e e e e s0stat address: s0stat 421 bit addressable reset value: 00h lsb msb figure 15. serial port extended status (s0stat) register note: see also figure 17 regarding framing error flag. uart interrupt scheme there are separate interrupt vectors for uart0 transmit and receive functions (see table 12 below). table 12. vector locations for uart in xa vector address interrupt source arbitration 00a0h 00a3h uart 0 receiver 10 00a4h 00a7h uart 0 transmitter 11 note: the transmit and receive vectors could contain the same isr address to work like an 8051 interrupt scheme. multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th one goes into bit rb_8 (s0con[2]). then comes a stop bit. uart0 can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb_8 = 1. this feature is enabled by setting bit sm2_0 (s0con[5]). a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2_0 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2_0 bit and prepare to receive the data bytes that will be coming. the slaves that weren't being addressed leave their sm2_0 bits set and go on about their business, ignoring the incoming data bytes. sm2_0 has no effect in uart mode 0, and in uart mode 1 can be used to check the validity of the stop bit although this is better done with the framing error flag (fe0) {s0stat[3]}. in a mode 1 reception, if sm2_0 = 1, the receive interrupt will not be activated unless a valid stop bit is received. error handling, status flags and break detect uart0 has the four error flags as described in figure 15. automatic address recognition automatic address recognition is a feature which allows uart0 to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2_0 bit. in the 9bit uart modes (mode 2 and mode 3) the receive interrupt flag (ri_0) (s0con[0]) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 16. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 22 using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, s0addr, and the address mask, s0aden. s0aden is used to define which bits in the s0addr are to be used and which bits are adon't careo. the s0aden mask can be logically anded with the s0addr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 s0addr = 1100 0000 s0aden = 1111 1101 given = 1100 00x0 slave 1 s0addr = 1100 0000 s0aden = 1111 1110 given = 1100 000x in the above example s0addr is the same and the s0aden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 s0addr = 1100 0000 s0aden = 1111 1001 given = 1100 0xx0 slave 1 s0addr = 1110 0000 s0aden = 1111 1010 given = 1110 0x0x slave 2 s0addr = 1110 0000 s0aden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of s0addr and s0aden. zeros in this result are treated as don'tcares. in most cases, interpreting the don'tcares as ones, the broadcast address will be ff hexadecimal. upon reset, s0addr and s0aden are loaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. bit symbol function s0con.5 sm2_0 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2_0 is set to 1, then ri_0 will not be activated if the received 9th data bit (rb8_0) is 0. in mode 1, if sm2_0=1 then ri_0 will not be activated if a valid stop bit was not received. in mode 0, sm2_0 should be 0. s0con.4 ren_0 enables serial reception. set by software to enable reception. clear by software to disable reception. s0con.3 tb8_0 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. the tb8_0 bit is not double buffered. see text for details. s0con.2 rb8_0 in modes 2 and 3, is the 9th data bit that was received. in mode 1, if sm2_0=0, rb8_0 is the stop bit that was received. in mode 0, rb8_0 is not used. s0con.1 ti_0 transmit interrupt flag. set when another byte may be written to the uart transmitter. see text for details. must be cleared by software. s0con.0 ri_0 receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the end of the stop bit time in the other modes (except see sm2_0). must be cleared by software. where sm0_0, sm1_0 specify the serial port mode, as follows: sm0_0 sm1_0 mode description baud rate 0 0 0 shift register f osc /16 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 1 1 3 9-bit uart variable su01330 ri_0 ti_0 rb8_0 tb8_0 ren_0 sm2_0 sm1_0 sm0_0 s0con address: s0con 420 bit addressable reset value: 00h lsb msb figure 16. serial port control (s0con) register philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 23 d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit su01331 e e e e fe0 br0 oe0 stint0 s0stat if 0, sets fe figure 17. uart framing error detection sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 s0con d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2_0 = 1: interrupt if ren_0=1, rb8_0=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2_0 to receive data bytes when all data bytes have been received: set sm2_0 to wait for next address. su01332 figure 18. uart multiprocessor communication, automatic address recognition input/output port pin configuration each i/o port pin can be userconfigured to one of four modes: quasibidirectional (essentially the same as standard 80c51 family i/o ports), opendrain, pushpull, and off (high impedance). after reset, the default configuration is quasibidirectional. i/o port pin configurations are determined by the settings in port configuration sfrs. there are two sfrs for each port, called pncfga and pncfgb, where ano is the port number. one bit in each of the two sfrs relates to the setting for the corresponding port pin, allowing any combination of the four modes to be mixed on any port pins. for instance, the mode of port 1 pin 3 (p1.3) is controlled by setting bit 3 (p1cfga[3] and p1cfgb[3]). table 13 shows the configuration register settings for the four port pin modes. the dc electrical characteristics of each mode may be found in table 19. table 13. port configuration register settings pncfgb pncfga port pin mode 0 0 opendrain 0 1 quasibidirectional 1 0 off (high impedance) 1 1 pushpull note: mode changes may cause glitches to occur during transitions. when modifying both registers, write instructions should be carried out consecutively. external bus if off chip code is selected (through the use of the ea/ pin), initial code fetches will be done within a full 20bit address space. the external program/data bus provides 16 bit width in a 20bit address space. reset refer to figure 19 for a recommended reset circuit example. v dd r c reset xa some typical values for r and c: r = 100k, c = 1.0 m f r = 1.0m, c = 0.1 m f (assuming that the v dd rise time is 1ms or less) su00702 figure 19. recommended reset circuit philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 24 rst/pin properties and requirements active low for improved noise immunity schmitt trigger with threshold = 0.7 vdd rst / must be low for the longer of 10 m s or 10 clocks if ea / = 1, all port pins are set to quasibidirectional mode if ea / = 0, all external bus pins are set to pushpull mode power-on reset must be > 10 msec to allow the onchip oscillator to stabilize other reset effects register file is zeroed except [r7] usp/ssp is set to 100h internal data ram is not affected all maskable interrupts are disabled ds, es, cs, ssel, pz, cm, pt0 and pt1 are zeroed the watchdog timer is turned on reset timing the ea / pin is sampled on the rising edge of the reset (rst / ) pulse. the result of this sampling determines whether the device is to begin execution from internal or external program memory. specifically, if ea / is pulled high, the xa starts in singlechip mode. lastly, after rst / is released, the {wait ; v pp ; ea / } pin becomes a bus wait signal for external bus transactions. p3.5 is weakly pulled high whenever rst/ is asserted. given ea/ is used at reset to request code starts from external memory, this weak pull up assures the pxac3 will setup a 16 bit external bus. thus, if external code operation is desired, the user must never put a low on p3.5 during reset. note: ea/ must be held for eight equivalent oscillator clock periods after rst/ is deasserted (i.e., after rst/ returns to one) to guarantee that the desired ea/ value is latched correctly. the relationship of ea/ timing with respect to both rst/ and ale signals is shown in figure 20. rst/ ea/ ale < 1 clk at least 8 equivalent clk periods at least 5 equivalent clk periods ea/ held stable alternate aholdo reference su01333 figure 20. ea/ timing diagram power reduction modes the xac3 supports idle and powerdown modes of power reduction. the idle mode leaves some peripherals running to allow them to wake up the processor when an interrupt is generated. the powerdown mode stops the oscillator in order to minimize power. the processor can be made to exit powerdown mode via reset or one of the external interrupt inputs. in order to use an external interrupt to reactivate the xa while in powerdown mode, the external interrupt must be enabled and be configured to levelsensitive mode. in powerdown mode, the power supply voltage may be reduced to the ram keepalive voltage (2v), retaining the ram, register, and sfr values at the point where the powerdown mode was entered. interrupts interrupt types there are four types of interrupts: event interrupts service peripherals such as uarts and timers. software interrupts demote the priority level of a running event interrupt below the lowest event priority level (i.e., 9), thereby permitting lower priority event interrupts to run. trap interrupts accomplish multitasking services, such as rtos, via nonmaskable interrupts. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 25 exception interrupts process nonmaskable events, such as reset, stack overflow, and dividebyzero. the xac3 supports 42 vectored interrupts. these include 13 maskable event interrupts, 7 software interrupts, 16 trap interrupts, and 6 exception interrupts. the number of event interrupts is related to the number of onchip peripherals. the xac3 supports 13 maskable event interrupts. however, software, trap, and exception interrupts are standardized within the xa core. for core details refer to the xa user guide. interrupt structures four tables provide details of the xa-c3 interrupt structure. table 14 defines the sixteen interrupt priority levels table 15 describes the exception and trap interrupts table 16 explains the event interrupts table 17 lists the software interrupts event interrupt handling if a higher priority event occurs while a lower priority event is being serviced, the higher priority event takes over. when events of different priorities occur simultaneously, the highest priority event is serviced first. when events of equal priority occur simultaneously, arbitration ranking determines which event is serviced first. see table 15 and table 16. interrupt priority details each event interrupt has 8 priority levels. event interrupts may be individually masked by bits in sfr registers iel and ieh (see table 5). event interrupts can also be globally disabled via the ea bit (iel[7]). using 3bit subgroups, interrupt priority assignment (ipa) registers (ipa0, ipa1, ipa2, ipa4, ipa5, ipa6, and ipa7) assign 1 of 8 priority levels per event interrupt. a zero value assigns interrupt priority 0, in effect disabling an interrupt. the remaining seven priority levels are defined in table 14. table 14. interrupt priority levels priority level type of interrupt 15 event interrupt 14 event interrupt 13 event interrupt 12 event interrupt 11 event interrupt 10 event interrupt 9 event interrupt 8 7 software interrupt 6 software interrupt 5 software interrupt 4 software interrupt 3 software interrupt 2 software interrupt 1 software interrupt 0 interrupt disable note: 1. details of the priority scheme may be found in the xa user guide. table 15. exception and trap interrupt vectors description vector address arbitration ranking reset (h/w, watchdog, s/w) 0000 0003 0 (high) breakpoint (h/w trap 1) 0004 0007 1 trace (h/w trap 2) 0008 000b 1 stack overflow (h/w trap 3) 000c 000f 1 divide by 0 (h/w trap 4) 0010 0013 1 user reti (h/w trap 5) 0014 0017 1 trap 0 15 (software) 0040 007f 1 philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 26 table 16. event interrupt vectors description flag bit vector ad- dress enable bit interrupt priority arbitration ranking external interrupt 0 ie0 ; tcon[1] 00800083 ex0 ; iel[0] px0 ; ipa0[2:0] 2 timer 0 interrupt tf0 ; tcon[5] 00840087 et0 ; iel[1] pt0 ; ipa0[6:4] 3 external interrupt 1 ie1 ; tcon[3] 0088008b ex1 ; iel[2] px1 ; ipa1[2:0] 4 timer 1 interrupt tf1 ; tcon[7] 008c008f et1 ; iel[3] pt1 ; ipa1[6:4] 5 timer 2 interrupt tf2 ; t2con[7] or t2ex [p1.7] 1 or exf2 ; t2con[6] 00900093 et2 ; iel[4] pt2 ; ipa2[2:0] 6 (can) rx buffer full canintflg[2] 00940097 ebuff ; iel[5] pbuff ; ipa2[6:4] 7 serial port 0 rx ri_0 ; s0con[0] 00a000a3 eri0 ; ieh[0] pri0 ; ipa4[2:0] 10 serial port 0 tx ti_0 ; s0con[1] 00a400a7 eti0 ; ieh[1] pti0 ; ipa4[6:4] 11 spi interrupt spfg ; spics[3] 00ac00af espi ; ieh[3] pspi ; ipa5[6:4] 13 (can) frame error canintflg[4] 00b000b3 ecer ; ieh[4] pcer ; ipa6[2:0] 14 (can) message error canintflg[3] 00b400b7 emer ; ieh[5] pmer ; ipa6[6:4] 15 (can) tx message complete canintflg[1] 00b800bb emti ; ieh[6] pmti ; ipa7[2:0] 16 (can) rx message complete canintflg[0] 00bc00bf emri ; ieh[7] pmri ; ipa7[6:4] 17 note: 1. when timer 2 is used as a baud rate generator, pin t2ex [p1.7] acts as an additional external interrupt. table 17. software interrupt vectors description request bit vector address enable bit interrupt priority software interrupt 7 swr7 ; swr[6] 0118011b swe7 ; swe[6] fixed at 7 (highest priority) software interrupt 6 swr6 ; swr[5] 01140117 swe6 ; swe[5] fixed at 6 software interrupt 5 swr5 ; swr[4] 01100113 swe5 ; swe[4] fixed at 5 software interrupt 4 swr4 ; swr[3] 010c010f swe4 ; swe[3] fixed at 4 software interrupt 3 swr3 ; swr[2] 0108010b swe3 ; swe[2] fixed at 3 software interrupt 2 swr2 ; swr[1] 01040107 swe2 ; swe[1] fixed at 2 software interrupt 1 swr1 ; swr[0] 01000103 swe1 ; swe[0] fixed at 1 (lowest priority) absolute maximum ratings table 18. absolute maximum ratings parameter rating unit operating temperature under bias 55 to +125 c storage temperature range 65 to +150 c voltage on ea / ; v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to v dd +0.5v v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 27 dc electrical characteristics table 19. dc electrical characteristics v dd = 4.5v to 5.5v unless otherwise specified; t ambient = 0 to +70 c for commercial, 40 c to +85 c for industrial, unless otherwise specified. symbol parameter test conditions limits unit min typ max supply currents i dd supply current, operating mode 32 mhz 54 80 ma i id supply current, idle mode 32 mhz 25 30 ma i pd powerdown mode current 5 100 m a i pdi powerdown mode current (40 c to +85 c) 150 m a inputs v ram ram keepalive voltage ram keepalive voltage 1.5 v v il input low voltage 0.5 0.22v dd v v ih input high voltage, except xtal1, rst / at 5.0v 2.2 v v ih1 input high voltage to xtal1, rst / at 5.0v 0.7v dd v v ol output low voltage all ports, ale, psen / 3 i ol = 3.2ma, v dd = 5.0v 0.5 v v oh1 output high voltage all ports, ale, psen / 1 i oh = 100ma, v dd = 4.5v 2.4 v v oh2 output high voltage, ports p03, ale, psen / 2 i oh = 3.2ma, v dd = 4.5v 2.4 v c io input/output pin capacitance 15 pf i il logical 0 input current, p03 6 v in = 0.45v 25 75 m a i li input leakage current, p03 5 v in = v il or v ih 10 m a i tl logical 1to0 transition current all ports 4 at 5.5v 650 m a can rxd v il input low voltage 0.5 0.22v dd v v ih input high voltage v dd = 5.0v 2.2 v c i input pin capacitance 15 pf i il logical 0 input current v in = 0.45v 25 75 m a i li input leakage current v in = v il or v ih 10 m a can txd v ol output low voltage i ol = 3.2ma, v dd = 5.0v 0.5 v v oh output high voltage i oh = 100ma, v dd = 4.5v 2.4 v c o output capacitance 15 pf i tl logical 1to0 transition current v dd = 5.5v 650 m a notes: 1. ports in quasibidirectional mode with weak pullup (applies to ale, psen / only during reset operations). 2. ports in pushpull mode, both pullup and pulldown are assumed to be of the same strength 3. in all output modes 4. port pins source a transition current when used in quasibidirectional mode and externally driven from 1 to 0. this current i s highest when v in is approximately 2v. 5. measured with port in highimpedance output mode. 6. measured with port in quasibidirectional output mode. 7. load capacitance for all outputs=80pf. 8. under steady state (nontransient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma (*note: this is 85 c specification for vdd = 5v.) maximum i ol per 8bit port: 26ma maximum total i ol for all outputs: 71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. see figures 29, 30, 32, and 33 for i dd test conditions, and figure 31 for i cc vs. frequency. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 28 ac electrical characteristics table 20. ac electrical characteristics v dd = 4.5v to 5.5v; t amb = 0 to +70 c for commercial, 40 c to +85 c for industrial. symbol figure parameter variable clock unit min max external clock f c oscillator frequency 0 32 mhz t c 22 clock period and cpu timing cycle 1/f c ns t chcx 22 clock high time t c * 0.5 ns t clcx 22 clock low time t c * 0.4 ns t clch 22 clock rise time 5 ns t chcl 22 clock fall time 5 ns address cycle t crar 21 delay from clock rising edge to ale rising edge 10 46 ns t lhll 16 ale pulse width (programmable) (v1 * t c ) 6 ns t avll 16 address valid to ale deasserted (setup) (v1 * t c ) 12 ns t llax 16 address hold after ale deasserted (t c /2) 10 ns code read cycle t plph 16 psen / pulse width (v2 * t c ) 10 ns t llpl 16 ale deasserted to psen / asserted (t c /2) 7 ns t aviva 16 address valid to instruction valid, ale cycle (access time) (v3 * t c ) 36 ns t avivb 17 address valid to instruction valid, nonale cycle (access time) (v4 * t c ) 29 ns t pliv 16 psen / asserted to instruction valid (enable time) (v2 * t c ) 29 ns t pxix 16 instruction hold after psen / deasserted 0 ns t pxiz 16 bus 3state after psen / deasserted (disable time) t c 8 ns t ixua 16 hold time of unlatched part of address after instruction latched 0 ns data read cycle t rlrh 18 rd / pulse width (v7 * t c ) 10 ns t llrl 18 ale deasserted to rd / asserted (t c /2) 7 ns t avdva 18 address valid to data input valid, ale cycle (access time) (v6 * t c ) 36 ns t avdvb 19 address valid to data input valid, nonale cycle (access time) (v5 * t c ) 29 ns t rldv 18 rd / low to valid data in, enable time (v7 * t c ) 29 ns t rhdx 18 data hold time after rd / deasserted 0 ns t rhdz 18 bus 3state after rd / deasserted (disable time) t c 8 ns t dxua 18 hold time of unlatched part of address after data latched 0 ns data write cycle t wlwh 20 wr / pulse width (v8 * t c ) 10 ns t llwl 20 ale falling edge to wr / asserted (v12 * t c ) 10 ns t qvwx 20 data valid before wr / asserted (data setup time) (v13 * t c ) 22 ns t whqx 20 data hold time after wr / deasserted (note 6) (v11 * t c ) 5 ns t avwl 20 address valid to wr / asserted (address setup time) (note 5) (v9 * t c ) 22 ns t uawh 20 hold time of unlatched part of address after wr / is deasserted (v11 * t c ) 7 ns wait input t wth 21 wait stable after bus strobe (rd / , wr / , or psen / ) asserted (v10 * t c ) 30 ns t wtl 21 wait hold after bus strobe (rd / , wr / , or psen / ) assertion (v10 * t c ) 5 ns notes: 1. load capacitance for all outputs = 80pf. 2. variables v1 through v13 reflect programmable bus timing, which is programmed via the bus timing registers (btrh and btrl). refer to the xa user guide for details of the bus timing settings. v1) this variable represents the programmed width of the ale pulse as determined by the alew bit in the btrl register. v1 = 0.5 if the alew bit = 0, and 1.5 if the alew bit = 1. v2) this variable represents the programmed width of the psen / pulse as determined by the cr1 and cr0 bits or the cra1, cra0, and alew bits in the btrl register. for a bus cycle with no ale, v2 = 1 if cr1/0 = 00, 2 if cr1/0 = 01, 3 if cr1/0 = 10, and 4 if cr1/0 = 11. note that during burst mode code fetches, psen / does not exhibit transitions at the boundaries of bus cycles. v2 still applies for the purpose of determining peripheral timing requirements. for a bus cycle with an ale, v2 = the total bus cycle duration (2 if cra1/0 = 00, 3 if cra1/0 = 01, 4 if cra1/0 = 10, and 5 if cra1/0 = 11) minus the number of clocks used by ale (v1 + 0.5). example: if cra1/0 = 10 and alew = 1, the v2 = 4 (1.5 + 0.5) = 2. v3) this variable represents the programmed length of an entire code read cycle with ale. this time is determined by the cra1 and cra0 bits in the btrl register. v3 = the total bus cycle duration (2 if cra1/0 = 00, 3 if cra1/0 = 01, 4 if cra1/0 = 10, and 5 if cra1/0 = 11). philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 29 v4) this variable represents the programmed length of an entire code read cycle with no ale. this time is determined by the cr1 and cr0 bits in the btrl register. v4 = 1 if cr1/0 = 00, 2 if cr1/0 = 01, 3 if cr1/0 = 10, and 4 if cr1/0 = 11. v5) this variable represents the programmed length of an entire data read cycle with no ale. this time is determined by the dr1 and dr0 bits in the btrh register. v5 = 1 if dr1/0 = 00, 2 if dr1/0 = 01, 3 if dr1/0 = 10, and 4 if dr1/0 = 11. v6) this variable represents the programmed length of an entire data read cycle with ale. the time is determined by the dra1 and dra0 bits in the btrh register. v6 = the total bus cycle duration (2 if dra1/0 = 00, 3 if dra1/0 = 01, 4 if dra1/0 = 10, and 5 if dra1/0 = 11). v7) this variable represents the programmed width of the rd / pulse as determined by the dr1 and dr0 bits or the dra1, dra0 in the btrh register, and the alew bit in the btrl register. for a bus cycle with no ale, v7 = 1 if dr1/0 = 00, 2 if dr1/0 = 01, 3 if dr1/0 = 10, and 4 if dr1/0 = 11. for a bus cycle with an ale, v7 = the total bus cycle duration (2 if dra1/0 = 00, 3 if dra1/0 = 01, 4 if dra1/0 = 10, and 5 if dra1/0 = 11) minus the number of clocks used by ale (v1 + 0.5). example: if dra1/0 = 00 and alew = 0, then v7 = 2 (0.5 + 0.5) = 1. v8) this variable represents the programmed width of the wrl / and/or wrh / pulse as determined by the wm1 bit in the btrl register. v8 1 if wm1 = 0, and 2 if wm1 = 1. v9) this variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by dw1 and dw0 or the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the value of v8. for a bus cycle with an ale, v9 = the total bus write cycle duration (2 if dwa1/0 = 00, 3 if dwa1/0 = 01, 4 if dwa1/0 = 10, and 5 if dwa1/0 = 11) minus the number of clocks used by the wrl / and/or wrh / pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1). example: if dwa1/0 = 10, wm0 = 1, and wm1 = 1, then v9 = 4 1 2 = 1. for a bus cycle with no ale, v9 = the total bus cycle duration (2 if dw1/0 = 00, 3 if dw1/0 = 01, 4 if dw1/0 = 10, and 5 if dw1/0 = 11) minus the number of clocks used by the wrl / and/or wrh / pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1). example: if dw1/0 = 11, wm0 = 1, and wm1 = 0, then v9 = 5 1 1 = 3. v10) this variable represents the length of a bus strobe for calculation of wait setup and hold times. the strobe may be rd / (for data read cycles), wrl / and/or wrh / (for data write cycles), or psen / (for code read cycles), depending on the type of bus cycle being widened by wait. v10 = v2 for wait associated with a code read cycle using psen / . v10 = v8 for a data write cycle using wrl / and/or wrh / . v10 = v71 for a data read cycle using rd / . this means that a single clock data read cycle cannot be stretched using wait. if wait is used to vary the duration of data read cycles, the rd / strobe width must be set to be at least two clocks in duration. also see note 4. v11) this variable represents the programmed write hold time as determined by the wm0 bit in the btrl register. v11 = 0 if the wm0 bit = 0, and 1 if the wm0 bit = 1. v12) this variable represents the programmed period between the end of the ale pulse and the beginning of the wrl / and/or wrh / pulse as determined by the data write cycle duration (defined by the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the values of v1 and v8. v12 = the total bus cycle duration (2 if dwa1/0 = 00, 3 if dwa1/0 = 01, 4 if dwa1/0 = 10, and 5 if dwa1/0 = 11) minus the number of clocks used by the wrl / and/or wrh / pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1), minus the width of the ale pulse (v1). example: if dwa1/0 = 11, wm0 = 1, wm1 = 0, and alew = 1, then v12 = 5 1 1 1.5 = 1.5. v13) this variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by dw1 and dw0 or the dwa1 and dwa0 bits in the btrh register), the wm0 bit in the btrl register, and the values of v1 and v8. for a bus cycle with an ale, v13 = the total bus cycle duration (2 if dwa1/0 = 00, 3 if dwa1/0 = 01, 4 if dwa1/0 = 10, and 5 if dwa1/0 = 11) minus the number of clocks used by the wrl / and/or wrh / pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1), minus the number of clocks used by ale (v1 + 0.5). example: if dwa1/0 = 11, wm0 = 1, wm1 = 1, and alew = 0, then v13 = 5 1 2 1 = 1. for a bus cycle with no ale, v13 = the total bus cycle duration (2 if dw1/0 = 00, 3 if dw1/0 = 01, 4 if dw1/0 = 10, and 5 if dw1/0 = 11) minus the number of clocks used by the wrl / and/or wrh / pulse (v8), minus the number of clocks used by data hold time (0 if wm0 = 0 and 1 if wm0 = 1). example: if dw1/0 = 01, wm0 = 1, and wm1 = 0, then v13 = 3 1 1 = 1. 3. not all combinations of bus timing configuration values result in valid bus cycles. refer to the xa user guide section on the external bus for details. 4. when code is being fetched for execution on the external bus, a burstmode fetch is used that does not have psen / edges in every fetch cycle. thus, if wait is used to delay code fetch cycles, a change in the loworder address lines must be detected to locate the beginning of a cycle. this would be a3 a1 while using an external 16 bit bus. 5. this parameter is provided for peripherals that have the data clocked in on the falling edge of the wr / strobe. this is not usually the case, and in most applications this parameter is not used. 6. please note that the xac3 requires that extended data bus hold time (wm0 = 1) to be used with external bus write cycles. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 30 t pxiz ale psen multiplexed address and data unmultiplexed address a1a3 t avll t pxix t llax instr in * t lhll t plph t plaz t llpl t aviva su00946 t pliv a4a19 t ixua * d0d15 figure 21. external program memory read cycle (ale cycle) ale psen multiplexed address and data unmultiplexed address a1a3 instr in * su01345 a4a19 t avivb * d0d15 a1a3 figure 22. external program memory read cycle (non-ale cycle) philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 31 ale multiplexed address and data unmultiplexed address rd data in * a4a19 a1a3 t llrl t rlrh t llax t avll t rhdx t rhdz t avdva t rldv su01346 t dxua * d0d15 figure 23. external data memory read cycle (ale cycle) t uawh t llax ale multiplexed address and data unmultiplexed address wrl or wrh a4a19 data out * a1a3 t llwl t wlwh t avll t avwl t qvwx t whqx su01347 * d0d15 figure 24. external data memory write cycle philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 32 xtal1 address bus wait su00709a t wtl ale bus strobe (wrl , wrh , rd , or psen ) t wth t crar (the dashed line shows the strobe without wait.) figure 25. wait signal timing v dd 0.5 0.45v 0.7v dd 0.2v dd 0.1 t chcl t c t clch t clcx t chcx su00842 figure 26. external clock drive v dd 0.5 0.45v 0.2v dd +0.9 0.2v dd 0.1 note: ac inputs during testing are driven at v dd 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at the 50% point of transitions. su00703a figure 27. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 28. float waveform philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 33 v dd ea rst xtal1 xtal2 v ss v dd (nc) clock signal su00591b figure 29. i dd test condition, active mode note: all other pins are disconnected v dd ea rst xtal1 xtal2 v ss v dd (nc) clock signal su00590b v dd figure 30. i dd test condition, idle mode note: all other pins are disconnected su01334 figure 31. i dd vs. frequency at v dd = 5.0v v dd 0.5 0.45v 0.7v dd 0.2v dd 0.1 t chcl t cl t clch t clcx t chcx su00608a figure 32. clock signal waveform for i dd tests in active and idle modes note: t clch = t chcl = 5 ns philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 34 v dd ea rst xtal1 xtal2 v ss (nc) su00585a v dd v dd figure 33. i dd test condition, power-down mode note: all other pins are disconnected. v dd =2v to 5.5v eprom characteristics the xac37 is programmed by using a modified improved quickpulse programming ? algorithm. this algorithm is essentially the same as that used by the later 80c51 family eprom parts. however, different pins are used for many programming functions. detailed eprom programming information may be obtained from the internet at www.philipsmcu.com/ftp.html. the xac3 contains three signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an xagx manufactured by philips. security bits with none of the security bits programmed the code in the program memory can be verified. when only security bit 1 (see table 21) is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory. all further programming of the eprom is disabled. when, in addition to the above, security bits 1 and 2 are programmed, verify mode is disabled. when all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. (see table 21). table 21. program security bits program lock bits sb1 sb2 sb3 protection description 1 u u u no program security features enabled. 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, external execution is disabled. internal data ram is not accessible. notes: 1. p programmed. u unprogrammed. 2. any other combination of the security bits is not defined. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 35 xa-c3 overview introduction the xa-c3 is a member of the philips xa (extended architecture) family of high performance 16bit singlechip microcontrollers. combined in the xa-c3 are an array of standard microcontroller peripherals, a powerful can 2.0a/b controller, and a unique can omessage managemento engine which provides integrated hardware support for most can t ransport l ayer (ctl ) protocols. integrated into the xa-c3 microcontroller is the can controller core from the awardwinning 1 philips sja1000 c an (2.0a/b) d ata l ink l ayer ( cdll ) device. since 1986, can users have developed highlevel can t ransport l ayers. the xa-c3 implements many such ctl concepts in hardware, including automatic assembly of multiframe fragmented messages. in fact, the xa-c3 is the first chip with hardware ctl support. the can module embedded in the xa-c3 provides far greater can functionality and power than any existing can product , including the sja 1000 itself . ctl protocols such as device net, canopen and osek deliver long messages distributed over many can frames (see figure 34). 1 c an i n a utomation 1997 this method is called fragmented (or, in european terminology, segmented) messaging. the individual frames, forming a complete ctl message, are interleaved on the can bus together with frames belonging to other (unrelated) ctl/can messages. the xa-c3 transparently reassembles up to 32 concurrent, interleaved ctl messages in hard ware as directed by a new, powerful id screener technology with 32 screeners and 32 dma channels. an onchip, 512byte, ctl/can message buffer ram provides singlechip storage for receive and transmit. this buffer ram is easily extended (offchip) to accommodate up to 32 messages of 256 bytes each. the xa-c3 provides these powerful can 2.0a/b and ctl features while maintaining pin and function compatibility with the present xa-g3; the new can rx/tx pins have been assigned to xa-g3 noconnects. thus, today's xa-g3 based products can incorporate ctl /can in new designs. xa-g3 software is preserved while xa-c3 features immediately upgrade present xa-g3 board layouts to ctl /can. additionally, the fullcan (can) features of the xa-c3 can be used independently of ctl . 8byte 8byte 8byte 8byte 8byte 8byte 8byte 8byte 8byte ctl messagea ctl messageb ctl messagec ctl messaged 8byte 8byte can data frame can bus su01335 figure 34. interleaved can data frames definition of terms standard and extended can frames see figure 35. acceptance filtering the process a can device implements (usually) in hardware to determine if a can frame should be accepted or ignored and, if accepted, to store that frame in a preassigned message object. message object a receive ram buffer of prespecified size (up to 256 bytes for ctl messages) and associated with a particular acceptance filter or, a transmit ram buffer which the user preloads with all necessary data to transmit a complete can data frame. can arbitration id an 11bit (standard can 2.0a frame) or 29bit (extended can 2.0b frame) identifier field placed in the can frame header. this id field is used to arbitrate frame access to the can bus. also used in acceptance filtering for can frame reception and transmit prearbitration. screener id a 30bit field extracted from the incoming message which is then used in acceptance filtering . the screener id includes the can arbitration id and the ide bit, and can include up to 2 data bytes. these 30 extracted bits are the information qualified by acceptance filtering . match id a 30bit field prespecified by the user to which the incoming screener i d is compared. individual match id s for each of the 32 objects are programmed by the user into designated memory mapped registers. mask a 29bit field prespecified by the user which can override ( mask ) a match id comparison at any particular bit (or, combination of bits) in an acceptance filter . individual mask s, one for each message object , are programmed by the user in designated mmr s. individual mask patterns assure that single receive objects can screen for multiple acknowledged ctl /can frames and thus minimize the number of receive objects that must be dedicated to such lower priority frames. this ability to mask individual message objects is an important new ctl feature. ctl can transport layer. a generic term for any highlevel protocol, which extends the capabilities of can while employing the can physical layer, can frame format and, adheres to the can philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 36 specification. among other things, can transport layers permit transmission of messages which exceed the 8 byte data limit inherent to can frames. fragmented message a lengthy message (in excess of 8 bytes) divided into data packets and transmitted using a sequence of individual can frames. the specific ways that sequences of can frames construct these lengthy messages is defined within the context of a specific can t ransport l ayer. the xa-c3 automatically reassembles these packets into the original, lengthy message in hardware and reports (via interrupt) when the completed message is available as an associated receive message object . message buffer a block of locations in xa data memory where incoming (received) messages are stored or where outgoing (transmit) messages are staged. mmr memory mapped register. an onchip command/control/status register whose address is mapped into xa data memory space and is accessed as data memory by the xa processor. bus idle sof 1bit can.id 11bits rtr 1bit ide 1bit r0 1bit dlc 4bit crc 15bits ack del 1bit bus idle sof 1bit base.id 11 msbs srr 1bit ide 1bit r0 1bit dlc 4bit extended.id 18 lsbs rtr 1bit r1 1bit eof 7bits ifs 3bits bus idle standard extended crc del 1bit ack 1bit crc 15bits ack del 1bit crc del 1bit ack 1bit rtr r emote t ransmit r equest srr s ubstitute r emote r equest ide id e xtension r1, r0 a r eservedo bits dlc d ata l ength c ode (0, 1, , 8) ifs i nter f rame s pace su01336 data field (0, 1, ..., 8 bytes) 0, 8, ..., 64-bits data field (0, 1, ..., 8 bytes) 0, 8, ..., 64-bits figure 35. can frame formats ctl/can functionality of the xa-c3 message objects / message management the xa-c3 allows the user to define up to 32 separate ctl/can message objects. any of these 32 objects can be designated as either a receive or transmit objects. any/all of the (up to 32) receive objects may be enabled to hardware assemble multi frame afragmentedo messages. for receive objects so enabled, ctl /can hardware interrupts the xa-c3 only at the completion of a multiframe message which is assembled in a contiguous fashion and stored in the receive message buffer associated with that object. at any given time, xa-c3 may actively assemble (up to) 32 interleaved ctl messages. receive objects may also be used as circular can frame buffers, to store up to 28 can frames of 8 data bytes each, between cpu interrupts. receive objects, not enabled to hardwareassemble messages, treat can2.0a/b frames as complete (singleframe) messages and are thus backward compatible with today's fullcan message objects that store single can frames. xa-c3 supports most ctl /can protocols, i.e., device.net, canopen and osek. generally, hardware amessagemanagemento on xa-c3 reduces the ctl instruction bandwidth of today's ctl message processing from 80% to as low as 10%. acceptance filtering the xa-c3 provides extensive id screening/filtering for 32 message objects. each object has a full 30 bits of filter match over the ctl /can id fields aswellas 29 bits of mask per object. that is, any combination of (up to) 30 bits in the id fields may be masked out ( adon't careo ) and/or matched on an objectbyobject basis . message storage each of the 32 message objects has its own designated message buffer space within the data memory space addressed by the xa processor. the size of each message buffer is independently user specified up to a max of 256 bytes/object. ctl messages that exceed the 256 byte/object limit can be accommodated with simple software intervention. the xa-c3 includes a 512 byte, onboard message buffer ram where some (or all) of the 32 (rx/tx) message buffers may reside. message buffer ram can be mapped anywhere in the 16 mbyte data memory space addressed by the xa and can be extended offchip to a maximum of 8 kbytes. this offchip expansion ability can accommodate up to thirtytwo, 256byte message buffers. transmit prearbitration two (2) options are available to prearbitrate among pending (currently enabled) transmit objects. a default option selects and transmits the object of highestpriority can arbitration id (the same criteria that arbitrates access to can bus itself). transmit object number serves as a secondary tiebreaker for queued transmit philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 37 objects having the same id. an alternate option bases transmit prearbitration exclusively on transmit object number, i.e., independent of arbitration id. remote frame handling the xa-c3 supports remote can frames. memory maps data memory space 1k byte of internal data memory (scratch pad) populates the very bottom of data memory space, in segment 0 by definition. the memory mapped registers and the onchip xram can also be mapped into segment 0 (as shown in figure 36), or into any other segment. 4k bytes mmr base address xram base address 000000h 00ffffh offchip onchip data memory (scratch pad) 0003ffh offchip 512 bytes offchip mmr space xram data memory segment 0 su01337 figure 36. mmrs and xram mapped into segment 00h. code memory space 32k bytes of internal code memory populate addresses 000000h 007fffh of code memory space. as shown in figure 37, code memory can be extended offchip, if desired, starting at address 008000h. the code memory address space extends to 0fffffh. 000000h 0fffffh offchip internal code memory 007fffh code memory 008000h su01338 figure 37. external code memory starts at 008000h. can core block (ccb) can bus timing can system clock the ccb has a programmable internal system clock, whose period is denoted by tscl. the can system clock is derived from the xa oscillator clock based on the following expression: tscl =2 * tclk * (32 * brp.5 + 16 * brp.4 + 8 * brp.3 + 4 * brp.2 + 2 * brp.1 + brp.0 + 1) where tclk is the period of the xa oscillator clock, and brp.5 brp.0 are bits in the mmr can b us t iming r egister (canbtr). the length of a bit period in a can frame is expressed in terms of number of can system clocks. samples per bit the number of samples per bit is determined by the value of the sam bit in canbtr. sam = 0 the bus is sampled once per bit (as shown below) sam = 1 the bus is sampled three times per bit (as shown below) philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 38 location of sample point the location of the sample point within a bit period is determined according to the following: one bit period tsync seg tseg1 tseg2 sample point su01339 tsyncseg = tscl tseg1 = tscl * (8 * tseg1.3 + 4 * tseg1.2 + 2 * tseg1.1 + tseg1.0 + 1) tseg2 = tscl * (4 * tseg2.2 + 2 * tseg2.1 + tseg2.0 + 1) where tseg1.3 tseg1.0 and tseg2.2 tseg2.0 are bits in canbtr. synchronization jump width to compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must resynchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum number of can system clock cycles that a bit period may be shortened or lengthened by one resynchronization, and is given by the following expression: tsjw = tscl * (2 * sjw.1 + sjw.0 + 1) where sjw.1 and sjw.0 are bits in canbtr. canbtr: can bus timing register address: mmr base + 272h access: read, write during reset mode only. word access only. reset value: 0000h canbtr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sam tseg2.2 tseg2.1 tseg2.0 tseg1.3 tseg1.2 tseg1.1 tseg1.0 sjw.1 sjw.0 brp.5 brp.4 brp.3 brp.2 brp.1 brp.0 can command and status registers two modes in can core operation the ccb has two different modes of operation: reset mode, and operation mode. on hardware reset, the can core is in reset mode, and the rr bit of cancmr ( can c o m mand r egister) will be set. the user application would usually set up registers, etc., then put the ccb into operation mode by clearing the rr bit. while in operation mode, the following conditions will cause the rr bit to be set, putting the ccb back into reset mode: tx buffer underflow (tbuf) bus off hardware reset test mode (refer to xa-c3 user guide, sections 2.2.2.1 and 2.7.1.2) cancmr: can command register address: mmr base + 270h access: read/write, no r/m/w, byte or word access. hardware can set bit 0. reset value: 01h cancmr 7 6 5 4 3 2 1 0 rxp st lo reserved slpen oc1 reserved rr rxp rx polarity, writable during reset mode only. 0 = noninverted, 1 = inverted. st self test, disable txack lo listen only reserved reserved bit. slpen ctl will go back to idle if no interrupt is generated. oc1 output control for tx pad. 0 = pushpull, 1 = open drain reserved reserved bit rr reset request. canstr: can status register address: mmr base + 271h access: read only, no write, no r/m/w. byte access ok. hardware can set or clear bits 7 2. reset value: 00h canstr 7 6 5 4 3 2 1 0 bs ep ew ts rs slpok bs bus status ep error passive ew error warning ts transmit status rs receive status slpok can status: no can bus activity and no pending core interrupts philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 39 can/ctl message handler message objects the xa-c3 supports 32 independent message objects, each of which can be either a transmit or a receive object. a receive object can be associated either with a unique can id, or with a set of can ids which share certain id bit fields. each message object has access to its own block of data memory space, which is known as the object's message buffer. both the size and base address of an object's message buffer is programmable. however, all message buffers must reside in the same 64kbyte segment of data memory, as the contents of a single register (mbxsr message buffer and xram segment register) are used to form the most significant byte of all 24bit message buffer addresses. each message object is associated with a set of eight mmrs dedicated to that object. some of these registers function differently for tx than they do for rx objects. the names of the eight mmrs are 1. mnmidh message n match id high 2. mnmidl message n match id low 3. mnmskh message n mask high 4. mnmskl message n mask low 5. mnctl message n control 6. mnblr message n buffer location register 7. mnbsz message n buffer size 8. mnfcr message n fragment count register where n ranges from 0 to 31. in general, setting up a message object involves configuring some or all of its eight mmrs. additionally, there are several mmrs whose bits control global parameters that apply to all objects. table 22 summarizes the eight message object mmrs and their functions for receive and transmit objects. details can be found in the sections that follow. table 22. message object register functions for tx and rx message object register (n = 0 31) rx function tx function address offset mnmidh match id* [28:13] can id [28:13] n0h mnmidl match id* [12:0][ide][][] can id [12:0][ide][][] n2h mnmskh mask [28:13] dlc n4h mnmskl mask [12:0][][][] not used n6h mnctl control control n8h mnblr buffer base address [a15:a0] buffer base address [a15:a0] nah mnbsz buffer size buffer size nch mnfcr fragmentation count** not used neh * after reception, the actual incoming screener id (without regard to mask bits) will be stored by hardware in mnmidh and mnmid l for the benefit of the user application. ** typically written to only by hardware. exceptions are the canopen and osek protocols in which the user application must als o initialize this register. receive message objects and the receive process during reception, the xa-c3 will store the incoming message in a temporary (13byte) buffer. once it is determined that a complete, errorfree can frame has been successfully received, the xa-c3 will initiate the acceptance filtering (amask and matcho) process. if acceptance filtering produces a match with an enabled receive object's match id, the message is stored by the dma engine in that object's message buffer. acceptance filtering the xa-c3 will sequentially compare the 30bit screener id extracted from the incoming frame to the corresponding match id values specified in the mnmidh and mnmidl registers for all currently enabled receive objects. any of the bits which are masked will be excluded from this comparison. masking is accomplished on an objectbyobject basis by writing a logic `1' in the desired bit position(s) in the appropriate mnmskh or mnmskl register. any screener id bits which are not intended to participate in acceptance filtering for a particular object must be masked by the user (e.g., id bits 0 & 1 for a standard can frame, and possibly one or both data bytes). if the acceptance filter determines that there is a match between the incoming frame and any enabled receive object, the contents of the frame will be stored, via dma, into the designated message buffer space associated with that object. if there is a match to more than one message object, the frame will be considered to have matched the one with the lowest object number. to summarize, acceptance filtering proceeds as follows: the ascreener ido field is extracted from the incoming can frame. the screener id field is assembled differently for standard and extended can frames. the assembled screener id field is compared to the match id fields of all enabled receive message objects. any bits which an object has masked (by having `1' bits in its mask field) are not included in the comparison. that is, if there is a `1' in some bit position of an object's mask field, the corresponding bit in the object's match id field becomes a don't care (i.e., always yields a match with the screener id). if filtering in this manner produces a match, the frame will be stored via the dma engine in that object's message buffer. if there is a match with more than one object, the frame will be considered to have matched the one with the lowest object number. screener id field for standard can frame the following table shows how the screener id field is assembled from the incoming bits of a standard can frame, and how it is compared to the match id and mask fields of object n. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 40 object n match id field (mnmidh and mnmidl) mid28 mid18 mid17 mid10 mid9 mid2 mid1 mid0 mide object n mask field (mnmskh and mnmskl) msk28 msk18 msk17 msk10 msk9 msk2 msk1 msk0 screener id field (assembled from incoming bitstream) can id.28 can id.18 data byte 1 [7:0] data byte 2 [7: 0] x x ide note: 1. for a standard can frame message object, only 27 bits plus ide (11 bits of can id + 2x8 bits + ide ) from the incoming messag e are routed to the acceptance filter. the user is therefore required to set the msk1 and msk0 bits in the mask field for that object (i.e., adon't careo). the ide bit is not maskable. in many applications based on standard can frames, either data byte 1, data byte 2, or both do not participate in acceptance filtering. therefore, the user is required to mask out the unused data byte(s). screener id field for extended can frame the following table shows how the screener id field is assembled from the incoming bits of an extended can frame, and how it is compared to the match id and mask fields of object n. note: the ide bit is not maskable. object n match id field (mnmidh and mnmidl) mid28 mid18 mid17 mid10 mid9 mid2 mid1 mid0 mide object n mask field (mnmskh and mnmskl) msk28 msk18 msk17 msk10 msk9 msk2 msk1 msk0 screener id field (assembled from incoming bitstream) can id.28 can id.0 ide mnmidh: message n match id high word address: mmr base + n0h access: read, write. word access only. reset value: xxxxh mnmidh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mid28 mid27 mid26 mid25 mid24 mid23 mid22 mid21 mid20 mid19 mid18 mid17 mid16 mid15 mid14 mid13 mnmidl: message n match id low word address: mmr base + n2h access: read, write. word access only. reset value: xxxxxxxxxxxxxx00b (unused bits are always read as `0') mnmidl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mid12 mid11 mid10 mid9 mid8 mid7 mid6 mid5 mid4 mid3 mid2 mid1 mid0 mide mnmskh: message n mask high word address: mmr base + n4h access: read, write. word access only. reset value: xxxxh mnmskh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msk28 msk27 msk26 msk25 msk24 msk23 msk22 msk21 msk20 msk19 msk18 msk17 msk16 msk15 msk14 msk13 note: 1. note: for transmit objects, the frame information is programmed in this register. mnmskl: message n mask low word address: mmr base + n6h access: read, write. word access only. reset value: xxxxxxxxxxxxx000b (unused bits are always read as `0') philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 41 mnmskl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msk12 msk11 msk10 msk9 msk8 msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 mnctl: message n control register address: mmr base + n8h access: read, write. byte or word access. reset value: 00000xxxb (unused bits are always read as `0') mnctl 7 6 5 4 3 2 1 0 obj_en int_en tx/rx frag rtr_en obj_en object enable. enables the message object for receive or transmit. 0 = disabled, 1 = enabled. int_en messagecomplete interrupt enable. specifies whether or not a tx or rx messagecomplete for this object will cause the object's messagecomplete interrupt to be generated. 0 = disabled, 1 = enabled. tx/rx transmit or receive. specifies whether this is a transmit or receive message object. 0 = transmit object, 1 = receive object. frag fragmented message enable. only relevant for receive message objects. enables automatic assembly of fragmented rx messages. if disabled, messages received by this object are assumed to be singleframe, or will be assembled by user software. 0 = disabled, 1 = enabled. note: masking of the can identifier field by user software, for the purpose of message object grouping, is disallowed for objects using hardware fragmentation assembly. however, masking of unused bit positions in the ascreenero, such is mandatory in all cases. rtr_en enable request to transmit. 0 = the object is not enabled for rtr handling, 1 = the object is enabled for rtr handling. see section entitled rtr handling , page 46. message storage when an incoming message frame has passed acceptance filtering, it will be automatically stored in data memory via dma. each message will be stored in its corresponding buffer area. on setup, the user is responsible for assigning a unique buffer location for each message object. this is specified in the object's mnblr register. the user is also required to set up the size of each buffer in the mnbsz register. the xa-c3 provides a total of 512 bytes of onchip message buffer ram (xram) which may contain part or all of the can/ctl (transmit & receive) message buffer space. see section entitled on-chip message buffer ram (xram) on page 55 for details. note: the following discussion concerning message buffer registers applies to transmit message retrieval as well as receive message storage. mbxsr (applies to all objects) address: mmr base + 291h access: read, write, byte or word reset value: ffh mbxsr 7 6 5 4 3 2 1 0 a23 a16 of all message buffer (and xram) base addresses all 32 message buffers must reside within the same 64k memory page. this page is specified by the contents of the mbxsr (message buffer and xram segment register) register. also, the 512 byte onchip message buffer ram (xram) is always positioned within that same 64k page pointed to by mbxsr. note: the xa-c3 brings out only 20 address lines to package pins. it can, therefore, only address 1mbyte of offchip data memory (a maximum of sixteen 64k segments). as a result, for the xa-c3, the four most significant bits of the mbsxr register must be set to `0000' if external ram is to be used for any portion of the message buffer space. mnbsz: message n buffer size register address: mmr base + nch access: readmodifywrite, byte or word access. reset value: 00000xxxb mnbsz 7 6 5 4 3 2 1 0 bsz.2 bsz.1 bsz.0 the size of an object's message buffer is specified with the 3bit field mnbsz[2:0] as shown in table 23. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 42 table 23. allowable message buffer sizes bsz.2 bsz.1 bsz.0 buffer size 0 0 0 2 bytes 0 0 1 4 bytes 0 1 0 8 bytes 0 1 1 16 bytes 1 0 0 32 bytes 1 0 1 64 bytes 1 1 0 128 bytes 1 1 1 256 bytes the user should bear in mind that only data bytes and (for rx only) a single byte of frame or bytecount information is stored in the message buffer. space does not need to be allocated for headers, fragmentation information, etc. see the rx memory buffer images below. mnblr: message n buffer location register address: mmr base + nah access: read, write. word access only. reset value: xxxxh mnblr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a15 a0 of object n message buffer base address the buffer location register holds the least significant 16 bits of the object's message buffer base address. the upper 8 bits of the 24bit address, for all message objects, are specified by the contents of mbsr. thus, the message buffers for all message objects must reside within the same 64kbyte segment. for any message buffer which is to be mapped into the onchip message buffer ram (xram), mnblr bits [15:9] must match xrambase bits [15:9]. important constraints: 256byte buffers must be located at a 256byte boundary (mnblr[7:0] = 00000000b) 128byte buffers must be located at a 128byte boundary (mnblr[6:0] = 0000000b) 2byte buffers must be located at a 2byte boundary (mnblr[0] = 0) note: message buffer logical address spaces must always adhere to the above constraints. however, there are at least two cases in which the user must initialize the mnblr register such that it does not point to the actual base location of the logical buffer space when reception begins. for details, please see sections entitled fragmented messages in osek on page 44 and fragmented messages in canopen on page 44. message assembly the dma will transfer the accepted message from the prebuffer to the message buffer area one word at a time, starting from the address pointed to by [mbxsr][mnblr]. every time dma transfers a byte or word, it has to request the bus. once granted, it will write data from the 13 byte receive prebuffer to memory. the dma will keep requesting the bus, writing message data sequentially to the memory until the whole frame is transferred. when dma has successfully transferred data from an incoming can message to memory, the contents of the receive buffer will depend on whether the message was nonfragmented (single frame) or fragmented. nonfragmented message assembly since masking is permitted on the 11 or 29bit can identifier for message objects with frag = 0, the complete can id for the incoming message is written into the mnmidh and mnmidl registers when the dma has completed. this will permit the user application to see the exact can identifier which resulted in the match. as a result of the above mechanism, the contents of mnmidh and mnmidl can change every time an incoming frame is accepted. since the incoming frame has to pass the match before it can be accepted, only the bits that are masked out will change. therefore, the criteria for match and mask will not change as a result of an accepted incoming frame (see figure 38). frame info direction of increasing dd data byte 1 address data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 figure 38. memory image for nonfragmented messages philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 43 the frame info byte contains the following bits: frame info 7 6 5 4 3 2 1 0 ide rtr sem1 sem0 dlc.3 dlc.2 dlc.1 dlc.0 the actual incoming screener id which caused the match can be retrieved from the mnmidh and mnmidl registers as shown in figure 39. mnmidh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 id.28 id.27 id.26 id.25 id.24 id.23 id.22 id.21 id.20 id.19 id.18 id.17 id.16 id.15 id.14 id.13 mnmidl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 id.12 id.11 id.10 id.9 id.8 id.7 id.6 id.5 id.4 id.3 id.2 id.1 id.0 ide figure 39. retrieving the screener id for an extended can frame fragmented message assembly masking of the 11/29 bit can identifier field by user software (but only the actual bits of the identifier itself!) is disallowed for any message object which employs autofragmentation assembly. the identifier which resulted in the match is, therefore, known unambiguously and is not included in the receive buffer. if the software needs access to this information, it can retrieve it from the appropriate mnmidh and mnmidl registers. as subsequent frames of a fragmented message are received, the new data bytes are appended to the end of the previously received packets. this process continues until a complete multiframe message has been received and stored. if an object is enabled with frag = 1, under protocols devicenet, canopen, and osek (prtcl1 prtcl0 00), the first can frame data byte is used to encode fragmentation information only. that byte will not be stored in the buffer area. the storage will start with the second data byte (data byte 2) and proceed to the end of the frame. see figure 40. byte count direction of increasing address data byte 2 a dd ress data byte 3 data byte dlc data byte 2 (next) data byte 3 (next) figure 40. memory image for fragmented ctl messages (frag = 1 and prtcl1 prtcl0 00) if an object is enabled with frag = 1, with can as the system protocol (prtcl1 prtcl0 = 00), then can frames are stored sequentially in that object's message buffer using the format shown in . also, if [prtcl1 prtcl0] = 00, rx buffer full is defined as aless than 9 bytes remainingo after storage of a complete can frame. when the dma pointer wraps around, it will be reset to offset `1' in the buffer, not offset `0', and there will be no byte count written. frameinfo direction of increasing address data byte 1 a dd ress data byte 2 data byte dlc frameinfo (next) data byte 1 (next) data byte 2 (next) direction of increasing dd direction of increasing dd figure 41. memory image for can frame buffering (frag = 1 and prtcl1 prtcl0 = 00) during buffer access, the dma will generate addresses automatically starting from the base location of the buffer. if the dma has reached the top of the buffer, but the message has not been completely transferred to memory yet, the dma will wrap around by generating addresses starting from the bottom of the buffer again. some time before this happens, a warning interrupt will be generated so that the user application can take the necessary action to prevent data loss. the top location of the buffer is determined by the size of the buffer as specified in mnbsz. the xa-c3 automatically receives, checks and reassembles up to 32 fragmented messages automatically. when the frag bit is set on a particular message, the message handler hardware will use the fragmentation information contained in data byte 1 of each frame. to enable automatic fragmented message handling for a certain message object, the user is responsible for setting the frag bit in the object's mnctl register. the message handler will keep track of the current address location and the number of bytes of each ctl message as it is being assembled in the designated message buffer location. after an aend of messageo is decoded, the message handler will finish moving the complete message and the byte count into the message buffer via philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 44 dma, and then interrupt the cpu that a complete message has been received. since data byte 1 of each frame contains the fragmentation information, it will never be stored in the ctl message buffer, thus each frame will have up to seven bytes of data stored. after the entire message is received, the message buffer will contain all of the actual informational data bytes received (exclusive of fragmentation information bytes) plus the byte count at location 00 which will contain the total number of informational data bytes stored. fragmentation error by looking at the fragmentation information, the message handler can determine the first frame , the middle frames, the end frame of the message, and each sequence number. in the case of canopen, there is no sequence number but rather a one bit field that toggles each frame. if a fragmentation error occurs, the message handler will reset the byte count, address pointer, and generate an interrupt to the cpu. at this point the ctl message buffer is determined to be invalid. fragmentation checking is disabled for all objects when can is the system protocol (prtcl[1:0] = 00). fragmentation error occurs only one way: 1. when the message handler receives a frame where the sequence number is not one greater than that of the previous frame. or in the case of canopen, the toggle bit has not toggled. fragmented messages in osek there are several important items that must be kept in mind with regard to hardware assembly of fragmented osek messages. for a complete discussion, please see the xa-c3 user manual. these items are summarized below: the osek firstframe cannot be treated as part of the fragmented message, but must be handled as a completely separate, singleframe, nonfragmented message. however, the firstframe may contain the first several bytes of userdata. for the object receiving the forthcoming message fragments, the mnfcr register must be initialized by the user to point at an address other than the buffer base location. this can be byte offset `1' or some other, more strategically chosen location. since there will be no firstframe received for this object, there will be no write of 00h to the buffer base location, by dma, at the beginning of the message. the fragment count register (mnfcr) of the object receiving the message fragments must be initialized by the user before enabling the object for receive. the initial value written to mnfcr must be identical to the sequencenumber of the first consecutiveframe that arrives (typically 0h). there is no alast frameo encoding for osek. therefore, there will be neither an rx message complete status flag, nor an interrupt, nor a byte count write associated with rx message complete, at the conclusion of a fragmented message. however, by carefully choosing the initial value for the mnblr register, the user can arrange to get an rx buffer full interrupt, and the associated rx buffer full byte count write, instead. fragmented messages in canopen in a canopen system, the software will need to write to the object`s fragment count register (mnfcr) to initialize the toggle bit prior to receiving the first frame of any new message which requires hardware fragmentation assembly. this bit will have to be initialized to the same state that will be received in the 1 st packet (typically 0). this bit will need to be initialized each time a new channel is established, even if none of the other parameters change (e.g., match, mask, buffer location, buffer size, etc.). since the hardware cannot detect a message start, there can be no semaphore write to the bottom of the buffer space at the start of a new fragmented message (for a discussion of the semaphore, see the section entitled using the semaphore bits, sem1 and sem0 on page 46. this location must still be left free for the hardware to write the byte count into at the end of the message. this means that for canopen fragmented messages (only fragmented) the software must initialize the address pointer to location `1' of the designated receive buffer, not location `0' as it does in devicenet. it also implies, of course, that the software loses the ability to check the semaphore to determine if message reconstruction is currently in progress. essentially, the hardware will treat the first frame of a multiframe canopen message exactly the same as intermediate frames. autoacknowledge in canopen a fragmented (segmented) canopen message may need to be acknowledged on a frame by frame basis. the xa-c3 provides hardware support for this process, with no cpu intervention. of course the user may elect not to autoacknowledge, or to implement the acknowledge function in software. suppose message object n ( n = 0 31) is enabled for receive, with the frag bit set. if the high level protocol is canopen, as selected in the gctl register, then the following steps must be taken to ensure that canopen frames are automatically acknowledged: set the auto_ack bit in gctl. set up a transmit object sequential to the canopen receive object, i.e., the object number set to be n+1. set the frag bit for this object. it is important not to set the obj_en bit for the transmit message. with the above setup, the xa-c3 will automatically generate a transmit frame upon successful reception of a canopen frame. the user must setup the screener id for the tx frame in the m n+1 midh and m n+1 midl registers, the rtr bit in m n+1 cntl[0], and the dlc in m n+1 mskh[3:0]. the user must also store the proper aacknowledge byteo, as defined by the protocol specification, in byte offset 0 of the tx object's message buffer. bit position [4] is a don't care, because the xa-c3 will automatically insert the toggle bit value from the incoming frame into the toggle bit position of the outgoing autoacknowledge frame. the format for storing the acknowledge byte is shown below in table 24 (subject to change without notice by the cia). philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 45 table 24. format for storing the canopen acknowledge byte 7 6 5 4 3 2 1 0 byte offset 0 scs t = d.c. x x x x byte offset 1 byte offset 2 byte offset 3 byte offset 4 not used in the protocol byte offset 5 byte offset 6 byte offset 7 mnfcr: message n fragmentation count register address: mmr base + neh access: read, write. byte or word access. reset value: 00xxxxxxb (unused bits are always read as `0') mnfcr 7 6 5 4 3 2 1 0 count an object's fragmentation count register need not be configured by the user in devicenet systems. however, in canopen and osek systems, the user must initialize this register. gctl: global control byte (applies to all objects) address: mmr base + 27eh access: read, write, r/m/w, byte or word reset value: 00h gctl 7 6 5 4 3 2 1 0 auto_ack pre_arb prtcl1 prtcl0 auto_ack enables automatic acknowledge for canopen. 0 = disable, 1 = enable. pre_arb establishes the transmit prearbitration scheme. 0 = prearbitration based on can id, object number is secondary tiebreaker. 1 = prearbitration based on object number only. [prtcl1 prtcl0] indicates ctl protocol of the system (if any). 00 = can 01 = devicenet 10 = canopen 11 = osek transmit message objects and the transmit process in order to transmit a message, the xa application program needs to first assemble the complete message and store it in the message buffer area for that message object (the address of the message buffer would have been previously programmed into the object's mnblr register). the header (can id and frame information) must be written to the object's mnmidh, mnmidl, and mnmskh registers as appropriate. when the above is done, the application is ready to transmit the message. to initiate a transmission, the object enable bit (obj_en) must be set (except when transmitting an autoacknowledge frame in canopen). this will allow this readytotransmit message to participate in the prearbitration process. if more than one message is ready to be transmitted. a socalled prearbitration process will be performed to determine which message object will be selected for transmission. there are two prearbitration policies which the user can choose between by setting or clearing the pre_arb bit in the gctl register. after a tx message complete, the tx prearbitration process is areseto, and begins again. also, if the winning message object subsequently loses arbitration on the can bus, the tx prearbitration process gets reset and begins again. if there is only one transmit message whose obj_en bit is set, it will be selected regardless of the prearbitration policy. prearbitration based on priority (default mode) this mode is selected by writing `0' to the pre_arb bit in gctl[2]. the filter state machine goes through all transmit message objects for which the obj_en bit is set. the message with the highest priority as defined by the can arbitration id field will be selected for transmission. if more than one pending transmit message share the same can identifier, then secondary priority will be based on xa-c3 message object numbers, with the lowest numbered object winning access. the winning message will then be output onto the can bus where it will compete for access with other transmitting nodes. prearbitration based on object number as an alternative, the user may select to base prearbitration on message object number alone. this mode is selected by writing `1' to the pre_arb bit in gctl[2]. the prearbitration state machine will go through the message objects sequentially, starting with object number 0, and select the first encountered transmit message object, with obj_en set to `1', for transmission. in other words, the order in which the messages objects are examined in the prearbitration process is by increasing object number n, where n = 0 31. each time prearbitration begins, the enabled message with the lowest object number will be selected philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 46 for transmission, regardless of the priority level represented by its can identifier. message retrieval once a message object is selected for transmission, the dma will begin retrieving the data from the message buffer area in memory and transferring the data to the can core block for transmission. the same dma engine and address pointer logic is used for message retrieval of transmit messages as for message storage of receive messages. message buffer location and size information is specified in the same way. please refer to the section entitled message storage on page 41 for a complete description. when a message is retrieved, it will be written to the ccb sequentially. during this process, the dma will keep requesting the bus, reading from memory and writing to the ccb. to prepare a message for transmission, the user application is required to put the message in the appropriate object's message buffer area in the format shown below: data byte 0 direction of increasing address data byte 1 a dd ress data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 please observe that the can identifier field and frame info must not be included in the transmit buffer. the transmit logic retrieves this information from the appropriate mnmidh, mnmidl, and mnmskh registers. the format for storing the frame information in the mnmskh register is shown in figure 42. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x dlc.3 dls.2 dlc.1 dlc.0 figure 42. format for storing the tx frame info in mnmskh transmission of fragmented messages the xa-c3 does not handle the transmission of fragmented messages in hardware. it is the user's responsibility to write each frame of a fragmented message to the transmit buffer, enable the object for transmission, and wait for a completion before writing the next frame to the message buffer. the user application must therefore transmit multiple frames one by one until the whole message is transmitted. however, by using multiple tx objects whose object numbers increase sequentially, and whose can ids have been configured identically, several frames of a fragmented message can be queuedup and enabled, and will be transmitted in order. rtr handling this section describes how to receive or transmit remote transmit request (rtr) frames. receiving an rtr frame 1. the software must setup an rx object with the rtr bit in mnctl[0] set to `1'. 2. an rtr frame is received when the can id matches that of the enabled receive object whose rtr bit set to `1'. 3. if interrupt is enabled for that message object, an interrupt will be generated upon the rtr message reception. 4. the software would usually have a transmit object available with the same id. upon receiving an rtr frame, the software should update the data for the corresponding transmit object and send it out. transmitting an rtr frame 1. the software must setup a tx object with the rtr bit in mnctl[0] set to `1'. 2. the software sets the object enable bit (obj_en) which will enable the object to participate in prearbitration. 3. after the object wins prearbitration, an rtr frame will be sent out with a `1' in the rtr bit position . 4. at the end of a successful rtr transmission, the obj_en bit will be cleared. an interrupt could be generated if it is enabled. 5. it is possible for an incoming message, with can id matching that of the transmitting rtr object, to arrive while the transmitting rtr object is in prearbitration, or even during transmission. in this case, the obj_en bit of the transmitting rtr object will be cleared to `0', but no interrupt will be generated. data integrity issues the data stored in the message buffer area can be accessed both by the cpu and by the dma engine. measures have been taken to ensure that the application does not read data from an object as it is being updated by the dma. this is especially important if receive interrupts have been disabled or have not been responded to before a new message could have arrived. the general principle is, when dma is accessing the buffer, the cpu should not attempt to read from and write to the buffer. when cpu is accessing the buffer, the dma is still allowed to access the buffer. when this happens the cpu should be able to detect and abandon the data read. using the semaphore bits, sem1 and sem0 a threestate semaphore is used to signal whether a given buffer is: 1. ready for cpu to read 2. being accessed by dma (therefore not ready for cpu read) 3. being read by cpu the semaphore is encoded by two semaphore bits, sem1 and sem0, which are in bit positions [5] and [4] of the frame info byte, the first byte of the receive buffer. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 47 at the start of a nonfragmented message, prior to writing any data bytes, the dma will begin by writing 01h into the first byte of the buffer (byte 0). once the complete frame has been stored, the dma will write the frame information into byte 0, with bits [5] and [4] always set to `1'. when the application wants to read from the object's buffer, it can read byte 0 to determine if the dma is currently updating the buffer. if byte 0 contains 01h, then the buffer is currently being updated. the application should not continue to read from the buffer. when the application starts to read from the buffer, it should set the semaphore to 10b. after reading is finished, the application should check the semaphore again. if it is still 10b, everything is ok. if, however, the semaphore becomes 01b or 11b after the cpu access is finished, it means that either the buffer is currently being accessed by dma or has been accessed by dma during the time the cpu was performing reads. in either case, the cpu should wait until the semaphore bits become 11b again, and reread. use of the semaphore bits is not mandatory. however, their use may help to maintain data consistency. there are no dedicated semaphore bits for use with fragmented messages. in the case of a fragmented message (in devicenet only), the dma will write a 00h in byte 0 of the object's buffer. after the completion of a ctl message, the byte count (1 to 255) will be written to byte 0. avoiding data corruption for transmit message objects to avoid data corruption when transmitting messages, there are three possible approaches: 1. if the message complete interrupt is enabled for the transmit message, the user application would write to the transmit buffer after seeing the interrupt. once the interrupt flag is set, it is known for sure that the pending message has already been transmitted. 2. wait until obj_en clears before writing to the buffer. this can be done by polling the obj_en bit. 3. clear obj_en, while the object is still in prearbitration. in the first two cases, the pending message will be transmitted completely before the next message gets sent. for the third case, the message will not be transmitted. instead, a message with new content will enter prearbitration. there is an additional mechanism that prevents corruption of a message that is being transmitted. if a transmission is ongoing for a message object, the xa-c3 hardware will prevent the user from clearing the obj_en bit in the object's mnctl register. osek, devicenet, and canopen frames of interest osek consecutiveframe data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 dlc user data 1 0 0 1 0 sn devicenet i/o message data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 dlc user data 1 fragment type fragment count fragment type = 00 fragment count = 0 ... this is the first fragment fragment count = 3f ... this is both the first and last fragment fragment type = 01 ... middle fragment fragment type = 10 ... last fragment canopen download domain segment request data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 dlc user data 1 ccs (user specified) t n (user specified) c c = 0 ... not last segment c = 1 ... last segment canopen autoacknowledge tx response to download domain segment data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 8 reserved 1 scs (user specified) t not used, always 0000 can/ctl related interrupts the can/ctl module will generate five different event interrupts to the xa core: rx message complete tx message complete rx buffer full message error frame error rx and tx message complete interrupts in the following discussion (and elsewhere in the document) the term amessageo applies to a complete transfer of information. for singleframe messages, the amessage completeo condition occurs at the end of the frame. for multiframe (fragmented) messages, message complete occurs after the last frame is received and stored. since the hardware doesn't recognize or handle fragmentation for transmit messages, the tx message complete philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 48 condition will always be generated at the end of each successfully transmitted frame. there is a control bit associated with each message object indicating whether a message complete condition should generate an interrupt, or just set a amessage complete status flago (for polling) without generating an interrupt. this is the int_en bit in the object's mnctl register, mnctl[3]. there are two 16bit mmrs, mcplh and mcpll, which contain the message complete status flags for all 32 objects. when a message complete (tx or rx) condition is detected for a particular message object, the corresponding bit in the mcplh or mcpll register will be set. this will occur regardless of whether the int_en bit is set for that object (in mnctl[3]), or whether message complete status flags have already been set for any other objects. in addition to these 32 message complete status flags, there is a tx message complete interrupt flag and an rx message complete interrupt flag (canintflg[1] and canintflg[0] respectively), which will generate the actual event interrupt requests to the xa core. when an end of message occurs , at the same moment that the message complete status flag is set, the appropriate tx or rx message complete interrupt flipflop will also be set provided that int_en = 1 for the object, and the interrupt is not already set and pending. the message complete interrupt flags should always be cleared using the 2step process outlined below: 1. message complete status flags for all interrupt enabled objects of that type (tx or rx) should first be cleared by writing `1' to their bit positions. 2. the message complete interrupt flag itself can now be cleared by writing `1' to its bit position. warning: message complete interrupt flags may be cleared before all message complete status flags for interrupt enabled objects of that type (rx or tx) are removed. however, the interrupt flag will not be reset to `1' by hardware, unless a new message complete condition occurs for some other interrupt enabled object. therefore, it is strongly recommended that message complete interrupt flags be cleared only after removing all message complete status flags for interrupt enabled objects of the same type, and at the end of the interrupt service routine. the newest addition is the m essage c omplete i nfo r egister (mcir). mcir[4:0] will encode the lowest object number of all objects whose int_en bits are set and who currently have a message complete condition (objects whose message complete status flags are set). a `1' in bit 5 means that one or more objects whose int_en bits are set have a message complete condition. a `0' in bit 5 means that no objects whose int_en bits are set have a message complete condition. bits 6 and 7 are unused. rx buffer full interrupt as successive frames of a fragmented message are transferred by dma into an object's message buffer, it is possible to reach the end of the designated buffer space before the complete message has been received. when this occurs, it is necessary for the processor to intervene in order that the remainder of the message be stored without any loss of data. if the system protocol is devicenet, canopen, or osek, then a message buffer is considered full when the number of bytes remaining in the buffer space, at the end of a complete frame , is less than seven. if the system protocol is can, i.e., [prtcl1 prtcl0] = 00, then rx buffer full is defined as aless than 9 bytes remainingo after storage of a complete can frame. when the dma pointer wraps around, it will be reset to offset `1' in the buffer, not offset `0', and there will be no byte count written. this condition could occur if the application has underestimated the message size, or deliberately established a small buffer to conserve memory. the condition will always occur with messages containing more than 255 data bytes (excluding fragmentation information bytes), since the maximum message buffer size is 256 bytes. the following discussion only applies to frames which are not the last frame of a message (which also, necessarily, excludes nonfragmented, singleframe messages). after dma of the last data byte of the frame is completed, a check will be performed to determine if the current byte count is less than 7 bytes from the end of the assigned message buffer. if it is, then there is the potential for the next frame to overrun the buffer. we will consider this alessthansevenbytesremainingo situation to be a bufferfull condition. when this condition is detected, the following will occur: the current byte count will be written into buffer location `0' except in can systems. if [prtcl1 prtcl0] = 00, no byte count will be written. the address pointer will be initialized to location `1' the rx buffer full interrupt will be generated as subsequent frames are received, the data bytes will be stored, beginning at location `1'. the semaphore byte will not be written to again, since message assembly is still in progress. once the endofmessage is finally received, the dmp will respond as usual, writing the bytecount to location `0' and setting the rx message complete interrupt flag. note that the byte count will now reflect the number of bytes received since the buffer wrapped around, not the total number of bytes in the message . software will have to calculate the difference. the software has two choices as to how to respond to this rx buffer full interrupt: 1. read the contents of the buffer, thereby freeing up space in the buffer for any remaining frames. 2. reposition the buffer by modifying the address pointer. note: the least significant bit of the address pointer will already be set to `1', and must remain so. the bottom location must be reserved for the bytecount which will be written at the end of the message. if option 1 is selected, the software will retrieve the current byte count from the bottom of the buffer. it will then retrieve the designated number of data bytes from the buffer. subsequent data received will be loaded into the buffer, beginning at location `1'. when the endofmessage occurs, the bytecount stored in location `0' will indicate how many new bytes have been received which must now be retrieved. for option 2, subsequent bytes will actually be written into a different buffer space, elsewhere in memory. the processor can wait until the entire message is received before retrieving any data. at that time, the `0' location of the 1 st buffer will indicate how many bytes are stored there, and likewise for the second buffer (or third or so on). note that option 2 is far more efficient and can be implemented with very few instructions. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 49 message error interrupt there are two possible sources of a message error interrupt: tx buffer underflow, and fragmentation error. when either of these conditions occur for any message object, the message error interrupt flag (canintflg[3]) will be set. in addition, the m essage e rror i nfo r egister (meir) will be updated to reflect the number of the object which suffered the message error, and the specific type of message error encountered (tx buffer underflow or fragmentation error). the merif interrupt flag is cleared by writing `1' to the flag's position in canintflg[3]. tx buffer underflow this condition occurs when the transmit engine is astarvedo due to the inability of the dma to gain access to the bus. this interrupt condition is predominantly for system debugging. it should never occur during normal operation unless there is a serious flaw in the system (e.g., a peripheral which asserts the wait signal for an extended period). fragmentation error fragmentation error is an outofsequence fragment count. for each successive frame of a fragmented message, the new fragment count must equal the previous count plus one. for devicenet, the fragment count field is 6 bits wide, for osek it is 4 bits wide, and for canopen it is merely a single, toggling bit. if a new startofmessage indicator is received for an object, while the xa-c3 is already in the process of assembling a message for that object, the pointers for that object will be automatically reset and assembly will recommence at the bottom of that object's message buffer. the previous, inprogress message will be overwritten, and no interrupt or error flag of any kind will be generated. frame error interrupt there are six conditions generated from within the can core, any of which may cause the frame error interrupt flag (the ferif bit in canintflg[4]) to be set: bus error prebuffer overflow arbitration lost error warning error passive bus off each condition has a corresponding status flag in the f rame e rror st atus r egister (festr), which will be set when that condition occurs. each condition also has a corresponding enable bit in the f rame e rror en able r egister (feenr). if a particular condition's enable bit is set, then when hardware sets that condition's status flag, the frame error interrupt flag will also be set. the frame error interrupt flag is cleared using a 2step process: 1. the six individual frame error status flags in the festr register must first be cleared. details on clearing these flags will be found in the following sections. 2. the ferif bit can then be cleared by writing `1' to the flag's bit position in canintflg[4]. bus error when a bus error occurs, the berr status flag in festr[3] will be set, generating a frame error interrupt, if enabled. the berr status flag is cleared by executing a read of the error code capture register (eccr). the type and location of the error within the bit stream will be encoded and stored in the error code capture register for the benefit of the user application. the eccr register must be read by the cpu in order to be reactivated for capturing the next error code, as well as to clear the berr status flag. error codes in the eccr register are interpreted as shown in table 25. a read of the eccr register should be executed before the bus error interrupt is enabled. table 25. error codes for the error code capture register (eccr) eccr[7:6] interpretation 00 bit error 01 form error 10 stuff error 11 other error eccr[5] interpretation 0 tx error, error occurred during transmission 1 rx error, error occurred during reception eccr[4:0] interpretation 00011 start of frame 00010 id28 id21 00110 id20 id18 00100 srr bit 00101 ide bit 00111 id17 id13 01111 id12 id5 01110 id4 id0 01100 rtr bit 01101 reserved bit 1 01001 reserved bit 0 01011 data length code 01010 data field 01000 crc sequence 11000 crc delimiter 11001 acknowledge slot 11011 acknowledge delimiter 11010 end of frame 10010 intermission (go buy popcorn) 10001 active error flag 10110 passive error flag 10011 tolerate dom bits 10111 error delimiter 11100 overload flag prebuffer overflow the xa-c3 stores one complete frame (which can be up to 13 bytes) in a receive aprebuffero while the previous frame is being processed. even under extreme conditions, this should provide ample time for the previous frame to be written to memory by dma. if for some reason the dma is unable to gain access to the bus for a long period of time, the prebuffer could overflow. in this event, the xa-c3 will stop accepting the new message. that is, once the five prebuffer bytes are full, subsequent incoming bits will be ignored. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 50 if the receive prebuffer overflows, the pbo status flag in festr[5] will be set, generating a frame error interrupt, if enabled. the pbo status flag is cleared by writing `1' to the flag's bit position. since this error will be generated before any acceptance filtering has been performed, there will be no message object number associated with the error (hence its inclusion under the category of frame error). note that the new message being ignored may be intended for some other device on the can bus. this error should never occur unless there is a serious systemdesign problem (e.g., an offchip device grabs the bus and fails to deassert awaito for an extended period). arbitration lost during transmission, arbitration on the can bus can be lost to a competing device with a higher priority can identifier. in this case, the arblst status flag in festr[4] will be set, generating a frame error interrupt if enabled. the arblst status flag is cleared by executing a read of the arbitration lost capture register. the bit position in the can identifier at which arbitration was lost will be encoded and stored in the arbitration lost capture register (alcr) for the benefit of the user application. the alcr must be read by the cpu in order to be reactivated for capturing the next arbitration lost code, as well as to clear the arblst status flag. the bit position in the can id is encoded and stored in the 5bit field alcr[4:0]. alcr[7:5] are reserved, and are always read as zeros. the 5bit number latched into alcr is interpreted according to table 26. table 26. arbitration lost codes alcr[4:0] interpretation 0 arbitration lost in id28 1 arbitration lost in id27 2 arbitration lost in id26 ... ... 10 arbitration lost in id18 11 arbitration lost in srr bit 12 arbitration lost in ide bit 13 arbitration lost in id17 (extended frame only) ... ... 30 arbitration lost in id0 (extended frame only) 31 arbitration lost in rtr bit (extended frame only) error warning the ew bit in canstr[5] reports the error status of the core, with regard to the error warning limit defined by the user. if ew is `0', then both the tx and rx error counters contain values less than that stored in the error warning limit register. if either counter reaches or exceeds the value stored in the ewlr register, then the ew bit will be set to `1'. subsequently if both counters decrement below the value stored in the ewlr register, the ew bit will be cleared to `0'. the errw status flag in festr[1] will be set each time the ew bit in canstr[5] changes state, generating a frame error interrupt, if enabled. that is, both the 0to1 and the 1to0 transitions of the ew bit will cause the errw status flag to be set. the errw status flag is cleared by writing `1' to the flag's bit position. error passive the ep bit in canstr[6] reflects the error passive status of the core. if either the tx or rx error counter equals or exceeds the predefined value 128d, the ep bit will be set to `1'. subsequently, if both counters decrement below 128d, the ep bit will be cleared to `0'. both 0to1 and 1to0 transitions of the ep bit will cause the errp status flag to be set, generating a frame error interrupt if enabled. the errp status flag is cleared by writing `1' to the flag's bit position in festr[0]. bus off the bs (bus status) bit in canstr[7] reflects the buson and busoff status of the core. bs = 0 means the can core is currently involved in bus activity (buson), while bs = 1 means it is not (busoff). when the transmit error counter exceeds the predefined value 255d, the bs bit is set to `1' (busoff). in addition, the rr bit is set to `1' (putting the can core into reset mode), and the boff status flag is set, generating a frame error interrupt if enabled. the transmit error counter is preset to 127d, and the receive error counter is cleared to 00h. the can core will remain in this state until it is returned to normal mode by clearing the rr bit. once the rr bit is cleared, the tx error counter will decrement once for each occurrence of the busfree signal (11 consecutive recessive bits). after 128 occurrences of busfree, the bs bit is cleared (buson). again, the boff status flag is set (generating another frame error interrupt if enabled). at this point, both the tx and rx error counters will contain the value 00h. at any time during the busoff condition (bs = 1), the cpu can determine the progress of the busoff recovery by reading the contents of the tx error counter. during busoff, a return to buson can be expedited under software control. if bs = 1, writing a value between 0 and 254 to the tx error counter and then clearing the rr bit will cause the bs bit to be cleared after only 1 occurrence of the busfree signal. as in the case above, on the 1to0 transition of the bs bit, the boff status flag will be set, generating another frame error interrupt if enabled. the cpu can also initiate a busoff condition, if the can core is first put into reset mode by setting rr = 1. next, the value 255 is written to the tx error counter, and the rr bit is cleared. with the core back in normal mode, the tx error counter contents are interpreted, and the busoff condition proceeds as described above, exactly as if it had been caused by bus errors. note that the tx error counter can only be written to when the can core is in reset mode, and that both 0to1 and 1to0 transitions of the bs bit will cause the boff status flag to be set, generating frame error interrupts if enabled. can interrupt registers canintflg (can interrupt flag register) address: mmr base + 228h access: read/clear, byte or word reset value: 00h canintflg 7 6 5 4 3 2 1 0 ferif merif rbfif tmcif rmcif ferif frame error interrupt flag (this bit is readonly, and must be cleared in festr) philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 51 merif message error interrupt flag (cleared by writing `1') rbfif rx buffer full interrupt flag (cleared by writing `1') tmcif transmit message complete interrupt flag (should be cleared using the 2step process described in the section entitled rx and tx message complete interrupts on page 47). rmcif receive message complete interrupt flag (should be cleared using the 2step process described in the section entitled rx and tx message complete interrupts on page 47 festr (frame error status register) address: mmr base + 22ch access: read, byte or word reset value: 00h festr 7 6 5 4 3 2 1 0 pbo arblst berr boff errw errp pbo frame error subtype is prebuffer overflow (cleared by writing `1') arblst frame error subtype is arbitration lost (cleared by reading the alcr register) berr frame error subtype is bus error (cleared by reading the eccr register) boff frame error subtype is bus off (cleared by writing `1') errw frame error subtype is error warning (cleared by writing `1') errp frame error subtype is error passive (cleared by writing `1') feenr (frame error enable register) address: mmr base + 22eh access: read, byte or word reset value: 00h feenr 7 6 5 4 3 2 1 0 pboe arblste berre boffe errwe errpe pboe prebuffer overflow enable (0 = disabled, 1 = enabled) arblste arbitration lost enable (0 = disabled, 1 = enabled) berre bus error enable (0 = disabled, 1 = enabled) boffe bus off enable (0 = disabled, 1 = enabled) errwe error warning enable (0 = disabled, 1 = enabled) errpe error passive enable (0 = disabled, 1 = enabled) mcir (message complete info register) address: mmr base + 229h access: read, byte or word reset value: 00h mcir 7 6 5 4 3 2 1 0 1 or more object number 1ormore 0 = no objects whose int_en bits are set currently have a message complete condition. 1 = one or more objects whose int_en bits are set currently have a message complete condition. object number these 5 bits encode the lowest object number (0 31) of all objects whose int_en bits are set and who currently have a message complete condition. if there are no such objects (1ormore = 0), these bits will be 00000b. meir (message error info register) address: mmr base + 22ah access: read, byte or word reset value: 00h meir 7 6 5 4 3 2 1 0 tbu frag rbf object number [tbu frag rbf] 001 = most recent is rx buffer full interrupt. 010 = most recent is fragmentation error interrupt. 100 = most recent is tx buffer underflow interrupt. object number these 5 bits encode the object number (0 31) of the message object experiencing the most recent message error (tx buffer underflow, fragmentation error, or rx buffer full) condition. if more than one object are encountering message errors, only the most recent object number will be available. mcplh (message complete status flags high) address: mmr base + 226h access: read/clear, byte or word reset value: 0000h philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 52 mcplh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 obj31 obj30 obj29 obj28 obj27 obj26 obj25 obj24 obj23 obj22 obj21 obj20 obj19 obj18 obj17 obj16 mcpll (message complete status flags low) address: mmr base + 224h access: read/clear, byte or word reset value: 0000h mcpll 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 obj15 obj14 obj13 obj12 obj11 obj10 obj9 obj8 obj7 obj6 obj5 obj4 obj3 obj2 obj1 obj0 txerc (tx error counter) address: mmr base + 274h access: read, write, r/m/w, byte or word reset value: 00h txerc 7 6 5 4 3 2 1 0 tc 7 tc 6 tc 5 tc 4 tc 3 tc 2 tc 1 tc 0 the tx error counter can only be written to when the can core is in reset mode. hardware will preset the register to 128 when a busoff condition occurs. see the section entitled bus off on page 50 for details. rxerc (rx error counter) address: mmr base + 275h access: read, write, r/m/w, byte or word reset value: 00h rxerc 7 6 5 4 3 2 1 0 rc 7 rc 6 rc 5 rc 4 rc 3 rc 2 rc 1 rc 0 the rx error counter can only be written to when the can core is in reset mode. when a busoff condition occurs, this register is cleared to 00h. ewlr (error warning limit register) address: mmr base + 276h access: read, write, r/m/w, byte or word reset value: 96h ewlr 7 6 5 4 3 2 1 0 ewl 7 ewl 6 ewl 5 ewl 4 ewl 3 ewl 2 ewl 1 ewl 0 eccr (error code capture register) address: mmr base + 278h access: read, write, r/m/w, byte or word reset value: 00h eccr 7 6 5 4 3 2 1 0 ec1 ec0 state the error code capture register contains detailed information about the most recent bus error. see table 25 for details. the register must be read in order to be reenabled for capturing the next error code, as well as to clear the berr status flag. this register should be read before enabling the bus error interrupt. alcr (arbitration lost capture register) address: mmr base + 27ah access: read, write, r/m/w, byte or word reset value: 00h alcr 7 6 5 4 3 2 1 0 bit number the alcr latches the bit number in the can identifier where the most recent arbitration lost occurred. see table 26 for details. the register must be read in order to be reenabled for capturing the next arbitration lost code, as well as to clear the arblst status flag. this register should be read before enabling the arbitration lost interrupt. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 53 can interrupt sfrs as with all xa event interrupts, the five can interrupts can be independently enabled, disabled, and prioritized using the interrupt control sfrs in the xa core (see ieh, iel, and ipa0 ipa7 in table 26 on page 50 and see table 16 on page 26). bit positions are given below in . table 27. sfr interrupt enable/priority bit positions note: also see table 25 on page 49 sfr name sfr address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ieh 427 emri emti emer ecer espi unused eti0 eri0 iel 426 ea unused ebuff et2 et1 ex1 et0 ex0 ipa0 4a0 pt0 px0 ipa1 4a1 pt1 px1 ipa2 4a2 pbuff pt2 ipa4 4a4 pti0 pri0 ipa5 4a5 pspi unused ipa6 4a6 pmer pcer ipa7 4a7 pmri pmti emri rx message complete interrupt enable. emti tx message complete interrupt enable. emer message error interrupt enable. ecer frame error interrupt enable. espi spi port interrupt enable. eti0, eri0 xa-c3 serial port 0 interrupt enable bits. ebuff rx buffer full interrupt enable. ea, et2, et1, ex1, et0, ex0 xa-c3 enable all, timer, and external interrupt enable bits. px0, pt0, px1, pt1, pt2 xa-c3 external and timer interrupt priority fields. pbuff rx buffer full interrupt priority field. pri0, pti0 xa-c3 serial port 0 interrupt priority fields. pspi spi port interrupt priority field. pmri rx message complete interrupt priority field. pmti tx message complete interrupt priority field. pmer message error interrupt priority field. pcer frame error interrupt priority field. powerdown and idle mode background: xa powerdown and idle modes powerdown mode on the xa means that the main oscillator is clampedoff and there is no chip activity of any kind. i dd in this mode is on the order of a few tens of microamps. wakeup from powerdown is accomplished via a system reset or a transition on the external interrupt 0 or 1 pins. the wakeup period is 10,000 oscillator clocks (enough for several can frames to be transmitted). idle mode on the xa means that the clocks are running but are gatedoff to the processor core. most peripherals are active, but some may be put to sleep along with the core. wakeup from idle mode is instantaneous, and is initiated via any interrupt. i dd in idle mode is in the range of 2530 ma @ 32 mhz if the can/ctl module is deactivated, perhaps 5480 ma @ 32 mhz if the can is left active. note that putting the xa core, by itself, into idle mode reduces power consumption by approximately 30 ma @ 32mhz. xa-c3 idle mode the default condition for the ctl/can module will be to stay awake in idle mode, so that the core can asleepo while can transmissions/receptions are in progress. any interrupt (e.g., message complete) will wake up the core. an option will be provided to include the can/ctl module in idle mode. this option will be selected in software by writing to the slpen bit in mmr cancmr[3]. if the can does go to sleep in idle mode, then any transition on the can rxd input pin will be asynchronously latched and will immediately reenable the clocks to the can/ctl module so that it can begin receiving the incoming frame. there will not be any interrupt generated, however, and the processor core will remain in idle mode. the cpu will only come out of idle mode once a complete message is received and stored and a messagecomplete interrupt is generated (unless, of course, some other system interrupt wakes it up prior to that). the ccb will generate a accb_idle_no signal which will be routed to all of the other can/ctl blocks (including the cmi) at the top level. xa-c3 powerdown mode if a transition of the can rxd input occurs when the xa-c3 is in powerdown mode, the cpu will enter idle mode (after a 9892 clock delay), and the ccb and message handler circuits will be activated to receive and process the incoming frame. when either of these blocks generates an interrupt (or some other enabled interrupt occurs), only then will the cpu come out of idle mode and begin executing code. code execution will resume either in the interrupt service routine, if its priority is higher than current code, or with the next instruction following the powerdown instruction. at this time the termination of the powerdown mode is actually complete. can sleep enable certain conditions must be met before the can/ctl module can be safely put to sleep (idle or powerdown). essentially, there must be no can activity in progress and no interrupts pending. the ccb must generate a asleepoko signal (slpok=canstr[2]) which indicates that these conditions are met. this signal must be used to enable the accb_idle_no signal. in addition, the asleepoko signal philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 54 must be readable by the processor as an mmr. if the processor is about to put the part into powerdown mode, it must read this bit first to determine if it is safe to do so. there is no need for the processor to read this bit prior to entering idle mode. the core is free to go into idle mode whenever it chooses. the can/ctl module will follow if and when it is ready. all of the logic required to implement everything discussed in this section will be in the ccb. memory interface unit general description the xa-c3 memory interface (mif) unit provides interfaces to generic memory devices such as sram, flash, and eprom. the timing of memory cycles, including different strobe widths, is programmable by software. mif arbitrates between memory accesses from the xa core and from the dma unit associated with the can/ctl function. it also provides access to the onchip memory mapped registers (mmrs) and the onchip message buffer ram (xram). summary of features supports generic memory including sram, flash, and eprom. programmable timing. supports wait states. static 16-bit bus sizing. arbitrates between cpu and dma access. relocatable memory mapped register (mmr) access for can/ctl related configuration and data. memory mapped registers (mmrs) the xa-c3 has several hundred bytes of memory mapped control/status registers (mmrs). these registers are mapped to the main data memory space. a 4kbyte space is reserved from the data memory space for memory mapped registers (mmrs). the base address of the mmr space is programmed by software. it can be placed anywhere within the entire 16 mbyte data memory space supported by the xa architecture, other than at the very bottom of memory (address 000000h) where it would conflict with the onchip data ram (scratch pad). the 4k mmr space will always start at a 4k boundary. the base address of the mmr space is determined by the contents of special function registers mrbl and mrbh, as shown in table 6 on page 11. any address asserted by the xa whose twelve most significant bits match the concatenation mrbh[7:0] mrbl[7:4] will be automatically routed to the onchip mmr bus. the reset values for mrbh and mrbl are 0fh and f0h respectively. therefore, after a reset the mmr space is mapped to the uppermost 4k bytes of data segment 0fh, but access to mmrs is disabled . the first 512 bytes (offset 000h 1ffh) of mmr space are the message object registers (eight per message object) for objects n = 0 31, as shown in figure mmr space 4k bytes segment xy in data memory space (ds = xy) mrbl[7:4]0000 mrbh[7:0] 00h a23 a16 a15 a0 a7 a8 xyffffh xy0000h su01340 figure 43. formation of the mmr base address philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 55 offset 000h mmr space offset fffh offset 1ffh 512 bytes object registers su01341 figure 44. detail of mmr space showing block of message object registers special function register mrbh address: sfr 497h reset value: 0fh mrbh 7 6 5 4 3 2 1 0 a23 a16 of mmr base address special function register mrbl address: sfr 496h reset value: f0h mrbl 7 6 5 4 3 2 1 0 a15 a12 of mmr base address mrbe mrbe mrbe is the global enable bit for mmrs. on reset, mrbe is cleared to 0. 0 = mmrs disabled 1 = mmrs enabled onchip message buffer ram (xram) the xa-c3 has a 512byte onchip message buffer ram (xram) which may contain part or all of the can/ctl (transmit & receive objects) message buffers. this block of memory can be accessed as regular data memory. the logic address of the xram is programmed by software, and must start at a 512byte boundary. the base address of the xram is determined by the contents of memory mapped registers mbxsr and xramb as shown in and . any address asserted by the xa core (or the dma) whose fifteen most significant bits match the concatenation mbxsr[7:0]xramb[7:1] will be automatically routed to the xram. on reset, the xram is disabled. note: the xram should not be confused with the 1k byte ascratchpado data ram which is also provided onchip . since the uppermost 8 bits of all message buffer addresses are formed by the contents of the mbxsr register, the xram and all 32 message buffers must reside in the same 64k byte data memory segment. since the xa-c3 only provides address lines a1 a19 for accessing external memory, all external memory addresses must be within the lowest 1m byte of address space. therefore, if there is external memory in the system into which any of the 32 message buffers will be mapped, then all 32 message buffers and the xram must also be mapped entirely into that same 64k byte segment, which must be below the 1m byte address limit. philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 56 xramb[7:1] 0 mbxsr[7:0] 00h xram 512 bytes segment xy in data memory space mnblr mbxsr[7:0] a23 a16 a15 a0 a7 a8 object n buffer size object n message buffer a23 a16 a15 a0 xyffffh xy0000h su01342 figure 45. formation of the xram base address, with object n message buffer mapped to offchip data memory. xramb[7:1] 0 mbxsr[7:0] 00h xram xram 512 bytes segment xy in data memory space a23 a16 a15 a0 a7 a8 mnblr mbxsr[7:0] object n buffer size object n message buffer a23 a16 a15 a0 xyffffh xy0000h su01343 figure 46. object n message buffer mapped into the onchip xram. mbxsr (message buffer and xram segment register) address: mmr base + 291h access: read, write. reset value: ffh mbxsr 7 6 5 4 3 2 1 0 a23 a16 of xram (and all message buffers) base address xramb (xram base address) address: mmr base + 290h access: read, write reset value: feh philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 57 xramb 7 6 5 4 3 2 1 0 a15 a9 of xram base address xre xre xram enable bit, resets to `0'. 0 = xram disabled 1 = xram enabled mif control and configuration registers mifcntl (sfr) address: sfr 495h mifcntl 7 6 5 4 3 2 1 0 waitd busd waitd wait disable 0 = wail enabled 1 = wait disabled busd external access disable 0 = enable 1 = disable mifbtrl (memory interface bus timing register low, mmr) address: mmr base + 292h access: read, write, byte or word reset value: efh mifbtrl 7 6 5 4 3 2 1 0 wm1 wm0 alew cr1 cr0 cra1 cra0 mifbtrh (memory interface bus timing register high, mmr) address: mmr base + 294h access: read, write, byte or word reset value: ffh mifbtrh 7 6 5 4 3 2 1 0 dw1 dw0 dwa1 dwa0 dr1 dr0 dra1 dra0 note: the two mmrs mifbtrl and mifbtrh are not to be confused with the two sfrs btrl and btrh, which control the operation of the biu, not the mif. in order for the mif to function properly, the contents of btrl and btrh have to be set at a fixed configuration on reset, by user application software, similar to the treatment for the xa-scc mif. bus arbitration bus arbitration is done on an aalternateo policy. after a dma bus access, the cpu will get the bus if requested. after a cpu bus access, the dma will get the bus if requested. a burst access from the cpu cannot be interrupted by a dma bus access. spi port the onchip spi port uses the following memory mapped registers: spicfg (mmr) address: mmr base + 260h access: read, write, byte or word reset value: 00h spicfg 7 6 5 4 3 2 1 0 spcp rsvd rsvd rsvd spc3 spc2 spc1 spc0 spcp spiclk polarity 0 = inverted spiclk 1 = normal spiclk rsvd reserved bits, only write zeros. spc3 spc0 spiclk timing spiclk = (cclk) / 4 (spicfg[3:0] + 1) spidata (mmr) address: mmr base + 262h access: read, write, byte or word reset value: 00h spidata 7 6 5 4 3 2 1 0 data spics (mmr) address: mmr base + 263h access: read, write, byte or word reset value: 00h philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 58 spicfg 7 6 5 4 3 2 1 0 spstt spb2 spb1 spb0 spfg rsvd rsvd spidl spstt spi start 0 = cycle finished, cleared by hardware and on reset 1 = start spb2 spb0 number of spi bits transceived = spicfg[6:4] + 1 rsvd reserved bits, write only zeros spidl spi txd idle state 0 = idle low 1 = idle high philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 59 lqfp44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 60 plcc44: plastic leaded chip carrier; 44 leads sot187-2 philips semiconductors preliminary specification xa-c3 xa 16-bit microcontroller family 32k/1024 otp can transport layer controller 1 uart, 1 spi port, can 2.0b, 32 can id filters, transport layer co-processor 2000 jan 25 61 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2000 all rights reserved. printed in u.s.a. date of release: 01-00 document order number: 9397 750 06805 data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design. |
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